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@@ -49,6 +49,11 @@ struct lcn_tx_iir_filter {
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u16 values[16];
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};
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+enum lcn_sense_type {
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+ B43_SENSE_TEMP,
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+ B43_SENSE_VBAT,
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+};
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+
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/* In theory it's PHY common function, move if needed */
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/* brcms_b_switch_macfreq */
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static void b43_phy_switch_macfreq(struct b43_wldev *dev, u8 spurmode)
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@@ -335,8 +340,12 @@ static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
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}
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/* wlc_lcnphy_vbat_temp_sense_setup */
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-static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
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+static void b43_phy_lcn_sense_setup(struct b43_wldev *dev,
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+ enum lcn_sense_type sense_type)
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{
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+ u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
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+ u16 auxpga_vmid;
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+ u8 tx_pwr_idx;
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u8 i;
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u16 save_radio_regs[6][2] = {
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@@ -351,21 +360,96 @@ static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
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};
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u16 save_radio_4a4;
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+ msleep(1);
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+
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+ /* Save */
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for (i = 0; i < 6; i++)
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save_radio_regs[i][1] = b43_radio_read(dev,
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save_radio_regs[i][0]);
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for (i = 0; i < 14; i++)
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save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
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+ b43_mac_suspend(dev);
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save_radio_4a4 = b43_radio_read(dev, 0x4a4);
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+ /* wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF); */
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+ tx_pwr_idx = dev->phy.lcn->tx_pwr_curr_idx;
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+
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+ /* Setup */
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+ /* TODO: wlc_lcnphy_set_tx_pwr_by_index(pi, 127); */
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+ b43_radio_set(dev, 0x007, 0x1);
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+ b43_radio_set(dev, 0x0ff, 0x10);
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+ b43_radio_set(dev, 0x11f, 0x4);
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+
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+ b43_phy_mask(dev, 0x503, ~0x1);
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+ b43_phy_mask(dev, 0x503, ~0x4);
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+ b43_phy_mask(dev, 0x4a4, ~0x4000);
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+ b43_phy_mask(dev, 0x4a4, (u16) ~0x8000);
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+ b43_phy_mask(dev, 0x4d0, ~0x20);
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+ b43_phy_set(dev, 0x4a5, 0xff);
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+ b43_phy_maskset(dev, 0x4a5, ~0x7000, 0x5000);
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+ b43_phy_mask(dev, 0x4a5, ~0x700);
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+ b43_phy_maskset(dev, 0x40d, ~0xff, 64);
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+ b43_phy_maskset(dev, 0x40d, ~0x700, 0x600);
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+ b43_phy_maskset(dev, 0x4a2, ~0xff, 64);
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+ b43_phy_maskset(dev, 0x4a2, ~0x700, 0x600);
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+ b43_phy_maskset(dev, 0x4d9, ~0x70, 0x20);
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+ b43_phy_maskset(dev, 0x4d9, ~0x700, 0x300);
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+ b43_phy_maskset(dev, 0x4d9, ~0x7000, 0x1000);
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+ b43_phy_mask(dev, 0x4da, ~0x1000);
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+ b43_phy_set(dev, 0x4da, 0x2000);
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+ b43_phy_set(dev, 0x4a6, 0x8000);
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+
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+ b43_radio_write(dev, 0x025, 0xc);
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+ b43_radio_set(dev, 0x005, 0x8);
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+ b43_phy_set(dev, 0x938, 0x4);
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+ b43_phy_set(dev, 0x939, 0x4);
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+ b43_phy_set(dev, 0x4a4, 0x1000);
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+
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+ /* FIXME: don't hardcode */
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+ b43_lcntab_write(dev, B43_LCNTAB16(0x8, 0x6), 0x640);
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+
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+ switch (sense_type) {
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+ case B43_SENSE_TEMP:
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+ b43_phy_set(dev, 0x4d7, 0x8);
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+ b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x1000);
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+ auxpga_vmidcourse = 8;
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+ auxpga_vmidfine = 0x4;
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+ auxpga_gain = 2;
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+ b43_radio_set(dev, 0x082, 0x20);
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+ break;
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+ case B43_SENSE_VBAT:
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+ b43_phy_set(dev, 0x4d7, 0x8);
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+ b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x3000);
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+ auxpga_vmidcourse = 7;
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+ auxpga_vmidfine = 0xa;
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+ auxpga_gain = 2;
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+ break;
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+ }
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+ auxpga_vmid = (0x200 | (auxpga_vmidcourse << 4) | auxpga_vmidfine);
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- /* TODO: config sth */
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+ b43_phy_set(dev, 0x4d8, 0x1);
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+ b43_phy_maskset(dev, 0x4d8, ~(0x3ff << 2), auxpga_vmid << 2);
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+ b43_phy_set(dev, 0x4d8, 0x2);
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+ b43_phy_maskset(dev, 0x4d8, ~(0x7 << 12), auxpga_gain << 12);
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+ b43_phy_set(dev, 0x4d0, 0x20);
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+ b43_radio_write(dev, 0x112, 0x6);
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+ /* TODO: dummy transmission? */
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+ /* Wait if not done */
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+ if (!(b43_phy_read(dev, 0x476) & 0x8000))
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+ udelay(10);
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+
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+ /* Restore */
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for (i = 0; i < 6; i++)
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b43_radio_write(dev, save_radio_regs[i][0],
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save_radio_regs[i][1]);
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for (i = 0; i < 14; i++)
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b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
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+ /* TODO: wlc_lcnphy_set_tx_pwr_by_index(tx_pwr_idx) */
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b43_radio_write(dev, 0x4a4, save_radio_4a4);
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+
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+ b43_mac_enable(dev);
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+
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+ msleep(1);
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}
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static bool b43_phy_lcn_load_tx_iir_cck_filter(struct b43_wldev *dev,
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@@ -499,7 +583,7 @@ static void b43_phy_lcn_tx_pwr_ctl_init(struct b43_wldev *dev)
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}
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b43_phy_lcn_set_tx_gain(dev, &tx_gains);
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b43_phy_lcn_set_bbmult(dev, bbmult);
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- b43_phy_lcn_sense_setup(dev); /* TODO: TEMPSENSE as arg */
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+ b43_phy_lcn_sense_setup(dev, B43_SENSE_TEMP);
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} else {
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b43err(dev->wl, "TX power control not supported for this HW\n");
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}
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