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@@ -106,34 +106,32 @@ nvc0_vram_init(struct drm_device *dev)
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
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const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
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- u32 parts = nv_rd32(dev, 0x121c74);
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+ u32 parts = nv_rd32(dev, 0x022438);
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+ u32 pmask = nv_rd32(dev, 0x022554);
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u32 bsize = nv_rd32(dev, 0x10f20c);
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u32 offset, length;
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bool uniform = true;
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int ret, part;
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NV_DEBUG(dev, "0x100800: 0x%08x\n", nv_rd32(dev, 0x100800));
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- NV_DEBUG(dev, "parts 0x%08x bcast_mem_amount 0x%08x\n", parts, bsize);
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+ NV_DEBUG(dev, "parts 0x%08x mask 0x%08x\n", parts, pmask);
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dev_priv->vram_type = nouveau_mem_vbios_type(dev);
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dev_priv->vram_rank_B = !!(nv_rd32(dev, 0x10f200) & 0x00000004);
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/* read amount of vram attached to each memory controller */
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- part = 0;
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- while (parts) {
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- u32 psize = nv_rd32(dev, 0x11020c + (part++ * 0x1000));
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- if (psize == 0)
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- continue;
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- parts--;
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-
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- if (psize != bsize) {
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- if (psize < bsize)
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- bsize = psize;
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- uniform = false;
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+ for (part = 0; part < parts; part++) {
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+ if (!(pmask & (1 << part))) {
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+ u32 psize = nv_rd32(dev, 0x11020c + (part * 0x1000));
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+ if (psize != bsize) {
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+ if (psize < bsize)
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+ bsize = psize;
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+ uniform = false;
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+ }
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+
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+ NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize);
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+ dev_priv->vram_size += (u64)psize << 20;
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}
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-
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- NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize);
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- dev_priv->vram_size += (u64)psize << 20;
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}
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/* if all controllers have the same amount attached, there's no holes */
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