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@@ -42,7 +42,6 @@ static struct clocksource nmdk_clksrc = {
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.rating = 200,
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.read = nmdk_read_timer_dummy,
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.mask = CLOCKSOURCE_MASK(32),
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- .shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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@@ -82,6 +81,12 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
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case CLOCK_EVT_MODE_UNUSED:
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/* disable irq */
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writel(0, mtu_base + MTU_IMSC);
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+ /* disable timer */
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+ cr = readl(mtu_base + MTU_CR(1));
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+ cr &= ~MTU_CRn_ENA;
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+ writel(cr, mtu_base + MTU_CR(1));
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+ /* load some high default value */
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+ writel(0xffffffff, mtu_base + MTU_LR(1));
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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@@ -98,7 +103,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
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static struct clock_event_device nmdk_clkevt = {
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.name = "mtu_1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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- .shift = 32,
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.rating = 200,
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.set_mode = nmdk_clkevt_mode,
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.set_next_event = nmdk_clkevt_next,
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@@ -151,6 +155,7 @@ void __init nmdk_timer_init(void)
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} else {
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cr |= MTU_CRn_PRESCALE_1;
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}
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+ clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
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/* Timer 0 is the free running clocksource */
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writel(cr, mtu_base + MTU_CR(0));
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@@ -158,7 +163,6 @@ void __init nmdk_timer_init(void)
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writel(0, mtu_base + MTU_BGLR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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- nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
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/* Now the scheduling clock is ready */
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nmdk_clksrc.read = nmdk_read_timer;
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@@ -175,8 +179,10 @@ void __init nmdk_timer_init(void)
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} else {
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cr |= MTU_CRn_PRESCALE_1;
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}
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+ clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
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+
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writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
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- nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
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+
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nmdk_clkevt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
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nmdk_clkevt.min_delta_ns =
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