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@@ -1711,7 +1711,8 @@ static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
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struct drm_display_mode *mode,
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struct drm_display_mode *other_mode)
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{
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- u32 tmp;
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+ u32 tmp, buffer_alloc, i;
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+ u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
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/*
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* Line Buffer Setup
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* There are 3 line buffers, each one shared by 2 display controllers.
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@@ -1726,16 +1727,30 @@ static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
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* non-linked crtcs for maximum line buffer allocation.
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*/
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if (radeon_crtc->base.enabled && mode) {
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- if (other_mode)
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+ if (other_mode) {
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tmp = 0; /* 1/2 */
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- else
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+ buffer_alloc = 1;
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+ } else {
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tmp = 2; /* whole */
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- } else
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+ buffer_alloc = 2;
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+ }
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+ } else {
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tmp = 0;
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+ buffer_alloc = 0;
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+ }
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WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
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DC_LB_MEMORY_CONFIG(tmp));
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+ WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
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+ DMIF_BUFFERS_ALLOCATED(buffer_alloc));
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+ for (i = 0; i < rdev->usec_timeout; i++) {
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+ if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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+ DMIF_BUFFERS_ALLOCATED_COMPLETED)
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+ break;
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+ udelay(1);
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+ }
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+
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if (radeon_crtc->base.enabled && mode) {
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switch (tmp) {
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case 0:
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