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@@ -67,21 +67,6 @@ static int __init pcibus_class_init(void)
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}
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postcore_initcall(pcibus_class_init);
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-/*
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- * Translate the low bits of the PCI base
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- * to the resource type
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- */
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-static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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-{
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- if (flags & PCI_BASE_ADDRESS_SPACE_IO)
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- return IORESOURCE_IO;
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-
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- if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
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- return IORESOURCE_MEM | IORESOURCE_PREFETCH;
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-
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- return IORESOURCE_MEM;
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-}
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-
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static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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{
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u64 size = mask & maxbase; /* Find the significant bits */
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@@ -100,17 +85,21 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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return size;
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}
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-static inline enum pci_bar_type decode_bar(struct pci_dev *dev,
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- struct resource *res, u32 bar)
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+static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
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{
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u32 mem_type;
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+ unsigned long flags;
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if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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- res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
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- return pci_bar_io;
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+ flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
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+ flags |= IORESOURCE_IO;
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+ return flags;
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}
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- res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
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+ flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
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+ flags |= IORESOURCE_MEM;
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+ if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
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+ flags |= IORESOURCE_PREFETCH;
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mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
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switch (mem_type) {
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@@ -120,14 +109,15 @@ static inline enum pci_bar_type decode_bar(struct pci_dev *dev,
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dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
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break;
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case PCI_BASE_ADDRESS_MEM_TYPE_64:
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- return pci_bar_mem64;
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+ flags |= IORESOURCE_MEM_64;
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+ break;
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default:
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dev_warn(&dev->dev,
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"mem unknown type %x treated as 32-bit BAR\n",
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mem_type);
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break;
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}
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- return pci_bar_mem32;
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+ return flags;
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}
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/**
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@@ -180,9 +170,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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l = 0;
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if (type == pci_bar_unknown) {
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- type = decode_bar(dev, res, l);
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- res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
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- if (type == pci_bar_io) {
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+ res->flags = decode_bar(dev, l);
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+ res->flags |= IORESOURCE_SIZEALIGN;
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+ if (res->flags & IORESOURCE_IO) {
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l &= PCI_BASE_ADDRESS_IO_MASK;
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mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
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} else {
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@@ -195,7 +185,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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mask = (u32)PCI_ROM_ADDRESS_MASK;
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}
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- if (type == pci_bar_mem64) {
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+ if (res->flags & IORESOURCE_MEM_64) {
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u64 l64 = l;
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u64 sz64 = sz;
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u64 mask64 = mask | (u64)~0 << 32;
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@@ -219,7 +209,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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goto fail;
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}
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- res->flags |= IORESOURCE_MEM_64;
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if ((sizeof(resource_size_t) < 8) && l) {
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/* Address above 32-bit boundary; disable the BAR */
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pci_write_config_dword(dev, pos, 0);
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@@ -245,7 +234,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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}
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out:
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- return (type == pci_bar_mem64) ? 1 : 0;
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+ return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
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fail:
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res->flags = 0;
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goto out;
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