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@@ -105,6 +105,83 @@ static struct sock_filter ptp_filter[] = {
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PTP_FILTER
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};
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+/**
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+ * ixgbe_ptp_setup_sdp
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+ * @hw: the hardware private structure
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+ *
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+ * this function enables or disables the clock out feature on SDP0 for
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+ * the X540 device. It will create a 1second periodic output that can
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+ * be used as the PPS (via an interrupt).
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+ *
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+ * It calculates when the systime will be on an exact second, and then
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+ * aligns the start of the PPS signal to that value. The shift is
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+ * necessary because it can change based on the link speed.
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+ */
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+static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
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+{
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+ struct ixgbe_hw *hw = &adapter->hw;
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+ int shift = adapter->cc.shift;
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+ u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
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+ u64 ns = 0, clock_edge = 0;
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+
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+ if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
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+ (hw->mac.type == ixgbe_mac_X540)) {
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+
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+ /* disable the pin first */
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+ IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
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+ IXGBE_WRITE_FLUSH(hw);
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+
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+ esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
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+
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+ /*
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+ * enable the SDP0 pin as output, and connected to the
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+ * native function for Timesync (ClockOut)
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+ */
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+ esdp |= (IXGBE_ESDP_SDP0_DIR |
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+ IXGBE_ESDP_SDP0_NATIVE);
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+
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+ /*
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+ * enable the Clock Out feature on SDP0, and allow
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+ * interrupts to occur when the pin changes
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+ */
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+ tsauxc = (IXGBE_TSAUXC_EN_CLK |
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+ IXGBE_TSAUXC_SYNCLK |
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+ IXGBE_TSAUXC_SDP0_INT);
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+
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+ /* clock period (or pulse length) */
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+ clktiml = (u32)(NSECS_PER_SEC << shift);
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+ clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
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+
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+ /*
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+ * Account for the cyclecounter wrap-around value by
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+ * using the converted ns value of the current time to
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+ * check for when the next aligned second would occur.
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+ */
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+ clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
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+ clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
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+ ns = timecounter_cyc2time(&adapter->tc, clock_edge);
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+
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+ div_u64_rem(ns, NSECS_PER_SEC, &rem);
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+ clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
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+
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+ /* specify the initial clock start time */
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+ trgttiml = (u32)clock_edge;
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+ trgttimh = (u32)(clock_edge >> 32);
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+
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+ IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
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+ IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
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+ IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
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+ IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
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+
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+ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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+ IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
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+ } else {
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+ IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
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+ }
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+
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+ IXGBE_WRITE_FLUSH(hw);
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+}
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+
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/**
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* ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
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* @cc: the cyclecounter structure
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@@ -198,6 +275,9 @@ static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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now);
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spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
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+
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+ ixgbe_ptp_setup_sdp(adapter);
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+
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return 0;
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}
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@@ -251,6 +331,7 @@ static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
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timecounter_init(&adapter->tc, &adapter->cc, ns);
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spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
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+ ixgbe_ptp_setup_sdp(adapter);
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return 0;
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}
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@@ -281,8 +362,9 @@ static int ixgbe_ptp_enable(struct ptp_clock_info *ptp,
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if (on)
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adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
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else
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- adapter->flags2 &=
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- ~IXGBE_FLAG2_PTP_PPS_ENABLED;
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+ adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
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+
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+ ixgbe_ptp_setup_sdp(adapter);
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return 0;
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default:
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break;
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@@ -305,109 +387,15 @@ void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
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struct ixgbe_hw *hw = &adapter->hw;
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struct ptp_clock_event event;
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- event.type = PTP_CLOCK_PPS;
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-
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- /* Make sure ptp clock is valid, and PPS event enabled */
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- if (!adapter->ptp_clock ||
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- !(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
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- return;
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-
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- if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) {
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- switch (hw->mac.type) {
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- case ixgbe_mac_X540:
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- ptp_clock_event(adapter->ptp_clock, &event);
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- break;
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- default:
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- break;
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- }
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- }
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-}
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-
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-/**
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- * ixgbe_ptp_enable_sdp
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- * @hw: the hardware private structure
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- * @shift: the clock shift for calculating nanoseconds
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- *
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- * this function enables the clock out feature on the sdp0 for the
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- * X540 device. It will create a 1second periodic output that can be
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- * used as the PPS (via an interrupt).
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- *
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- * It calculates when the systime will be on an exact second, and then
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- * aligns the start of the PPS signal to that value. The shift is
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- * necessary because it can change based on the link speed.
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- */
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-static void ixgbe_ptp_enable_sdp(struct ixgbe_hw *hw, int shift)
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-{
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- u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh;
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- u64 clock_edge = 0;
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- u32 rem;
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-
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switch (hw->mac.type) {
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case ixgbe_mac_X540:
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- esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
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-
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- /*
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- * enable the SDP0 pin as output, and connected to the native
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- * function for Timesync (ClockOut)
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- */
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- esdp |= (IXGBE_ESDP_SDP0_DIR |
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- IXGBE_ESDP_SDP0_NATIVE);
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-
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- /*
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- * enable the Clock Out feature on SDP0, and allow interrupts
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- * to occur when the pin changes
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- */
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- tsauxc = (IXGBE_TSAUXC_EN_CLK |
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- IXGBE_TSAUXC_SYNCLK |
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- IXGBE_TSAUXC_SDP0_INT);
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-
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- /* clock period (or pulse length) */
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- clktiml = (u32)(NSECS_PER_SEC << shift);
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- clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
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-
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- clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
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- clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
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-
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- /*
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- * account for the fact that we can't do u64 division
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- * with remainder, by converting the clock values into
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- * nanoseconds first
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- */
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- clock_edge >>= shift;
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- div_u64_rem(clock_edge, NSECS_PER_SEC, &rem);
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- clock_edge += (NSECS_PER_SEC - rem);
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- clock_edge <<= shift;
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-
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- /* specify the initial clock start time */
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- trgttiml = (u32)clock_edge;
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- trgttimh = (u32)(clock_edge >> 32);
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-
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- IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
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- IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
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- IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
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- IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
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-
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- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
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- IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
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-
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- IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_TIMESYNC);
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+ ptp_clock_event(adapter->ptp_clock, &event);
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break;
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default:
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break;
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}
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}
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-/**
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- * ixgbe_ptp_disable_sdp
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- * @hw: the private hardware structure
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- *
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- * this function disables the auxiliary SDP clock out feature
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- */
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-static void ixgbe_ptp_disable_sdp(struct ixgbe_hw *hw)
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-{
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- IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_TIMESYNC);
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- IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0);
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-}
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/**
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* ixgbe_ptp_overflow_check - delayed work to detect SYSTIME overflow
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@@ -822,9 +810,6 @@ void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
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if (adapter->cycle_speed == cycle_speed && timinca)
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return;
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- /* disable the SDP clock out */
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- ixgbe_ptp_disable_sdp(hw);
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-
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/**
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* Scale the NIC cycle counter by a large factor so that
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* relatively small corrections to the frequency can be added
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@@ -877,10 +862,6 @@ void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
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IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
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IXGBE_WRITE_FLUSH(hw);
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- /* now that the shift has been calculated and the systime
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- * registers reset, (re-)enable the Clock out feature*/
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- ixgbe_ptp_enable_sdp(hw, shift);
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-
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/* store the new cycle speed */
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adapter->cycle_speed = cycle_speed;
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@@ -901,6 +882,12 @@ void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
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ktime_to_ns(ktime_get_real()));
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spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
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+
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+ /*
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+ * Now that the shift has been calculated and the systime
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+ * registers reset, (re-)enable the Clock out feature
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+ */
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+ ixgbe_ptp_setup_sdp(adapter);
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}
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/**
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@@ -979,10 +966,11 @@ void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
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*/
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void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
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{
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- ixgbe_ptp_disable_sdp(&adapter->hw);
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-
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/* stop the overflow check task */
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- adapter->flags2 &= ~IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED;
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+ adapter->flags2 &= ~(IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED |
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+ IXGBE_FLAG2_PTP_PPS_ENABLED);
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+
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+ ixgbe_ptp_setup_sdp(adapter);
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if (adapter->ptp_clock) {
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ptp_clock_unregister(adapter->ptp_clock);
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