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@@ -44,61 +44,15 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
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static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
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(void (*)(unsigned long, unsigned long))0xdeadbeef;
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-static void compute_alias(struct cache_info *c)
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-{
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- c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
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- c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
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-}
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-
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-static void __init emit_cache_params(void)
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-{
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- printk("PVR=%08x CVR=%08x PRR=%08x\n",
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- ctrl_inl(CCN_PVR),
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- ctrl_inl(CCN_CVR),
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- ctrl_inl(CCN_PRR));
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- printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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- boot_cpu_data.icache.ways,
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- boot_cpu_data.icache.sets,
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- boot_cpu_data.icache.way_incr);
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- printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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- boot_cpu_data.icache.entry_mask,
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- boot_cpu_data.icache.alias_mask,
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- boot_cpu_data.icache.n_aliases);
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- printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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- boot_cpu_data.dcache.ways,
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- boot_cpu_data.dcache.sets,
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- boot_cpu_data.dcache.way_incr);
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- printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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- boot_cpu_data.dcache.entry_mask,
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- boot_cpu_data.dcache.alias_mask,
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- boot_cpu_data.dcache.n_aliases);
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-
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- /*
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- * Emit Secondary Cache parameters if the CPU has a probed L2.
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- */
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- if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
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- printk("S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
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- boot_cpu_data.scache.ways,
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- boot_cpu_data.scache.sets,
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- boot_cpu_data.scache.way_incr);
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- printk("S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
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- boot_cpu_data.scache.entry_mask,
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- boot_cpu_data.scache.alias_mask,
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- boot_cpu_data.scache.n_aliases);
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- }
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-
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- if (!__flush_dcache_segment_fn)
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- panic("unknown number of cache ways\n");
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-}
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-
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/*
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* SH-4 has virtually indexed and physically tagged cache.
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*/
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void __init sh4_cache_init(void)
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{
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- compute_alias(&boot_cpu_data.icache);
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- compute_alias(&boot_cpu_data.dcache);
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- compute_alias(&boot_cpu_data.scache);
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+ printk("PVR=%08x CVR=%08x PRR=%08x\n",
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+ ctrl_inl(CCN_PVR),
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+ ctrl_inl(CCN_CVR),
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+ ctrl_inl(CCN_PRR));
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switch (boot_cpu_data.dcache.ways) {
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case 1:
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@@ -111,11 +65,9 @@ void __init sh4_cache_init(void)
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__flush_dcache_segment_fn = __flush_dcache_segment_4way;
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break;
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default:
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- __flush_dcache_segment_fn = NULL;
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+ panic("unknown number of cache ways\n");
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break;
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}
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-
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- emit_cache_params();
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}
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/*
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