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@@ -72,10 +72,9 @@
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#define DEFAULT_TIMEOUT_INTERVAL HZ
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#define DEFAULT_TIMEOUT_INTERVAL HZ
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-#define FLAGS_FIRST 0x0001
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#define FLAGS_FINUP 0x0002
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#define FLAGS_FINUP 0x0002
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#define FLAGS_FINAL 0x0004
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#define FLAGS_FINAL 0x0004
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-#define FLAGS_FAST 0x0008
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+#define FLAGS_SG 0x0008
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#define FLAGS_SHA1 0x0010
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#define FLAGS_SHA1 0x0010
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#define FLAGS_DMA_ACTIVE 0x0020
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#define FLAGS_DMA_ACTIVE 0x0020
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#define FLAGS_OUTPUT_READY 0x0040
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#define FLAGS_OUTPUT_READY 0x0040
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@@ -83,13 +82,17 @@
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#define FLAGS_INIT 0x0100
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#define FLAGS_INIT 0x0100
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#define FLAGS_CPU 0x0200
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#define FLAGS_CPU 0x0200
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#define FLAGS_HMAC 0x0400
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#define FLAGS_HMAC 0x0400
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-
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-/* 3rd byte */
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-#define FLAGS_BUSY 16
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+#define FLAGS_ERROR 0x0800
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+#define FLAGS_BUSY 0x1000
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#define OP_UPDATE 1
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#define OP_UPDATE 1
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#define OP_FINAL 2
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#define OP_FINAL 2
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+#define OMAP_ALIGN_MASK (sizeof(u32)-1)
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+#define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
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+
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+#define BUFLEN PAGE_SIZE
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+
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struct omap_sham_dev;
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struct omap_sham_dev;
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struct omap_sham_reqctx {
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struct omap_sham_reqctx {
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@@ -97,8 +100,8 @@ struct omap_sham_reqctx {
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unsigned long flags;
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unsigned long flags;
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unsigned long op;
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unsigned long op;
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+ u8 digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
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size_t digcnt;
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size_t digcnt;
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- u8 *buffer;
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size_t bufcnt;
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size_t bufcnt;
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size_t buflen;
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size_t buflen;
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dma_addr_t dma_addr;
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dma_addr_t dma_addr;
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@@ -107,6 +110,8 @@ struct omap_sham_reqctx {
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struct scatterlist *sg;
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struct scatterlist *sg;
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unsigned int offset; /* offset in current sg */
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unsigned int offset; /* offset in current sg */
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unsigned int total; /* total request */
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unsigned int total; /* total request */
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+
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+ u8 buffer[0] OMAP_ALIGNED;
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};
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};
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struct omap_sham_hmac_ctx {
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struct omap_sham_hmac_ctx {
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@@ -136,6 +141,7 @@ struct omap_sham_dev {
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int irq;
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int irq;
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struct clk *iclk;
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struct clk *iclk;
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spinlock_t lock;
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spinlock_t lock;
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+ int err;
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int dma;
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int dma;
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int dma_lch;
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int dma_lch;
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struct tasklet_struct done_task;
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struct tasklet_struct done_task;
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@@ -194,53 +200,68 @@ static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
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static void omap_sham_copy_hash(struct ahash_request *req, int out)
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static void omap_sham_copy_hash(struct ahash_request *req, int out)
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{
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
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struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
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+ u32 *hash = (u32 *)ctx->digest;
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+ int i;
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+
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+ /* MD5 is almost unused. So copy sha1 size to reduce code */
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+ for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
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+ if (out)
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+ hash[i] = omap_sham_read(ctx->dd,
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+ SHA_REG_DIGEST(i));
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+ else
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+ omap_sham_write(ctx->dd,
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+ SHA_REG_DIGEST(i), hash[i]);
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+ }
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+}
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+
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+static void omap_sham_copy_ready_hash(struct ahash_request *req)
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+{
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+ struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
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+ u32 *in = (u32 *)ctx->digest;
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u32 *hash = (u32 *)req->result;
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u32 *hash = (u32 *)req->result;
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int i;
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int i;
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+ if (!hash)
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+ return;
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+
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if (likely(ctx->flags & FLAGS_SHA1)) {
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if (likely(ctx->flags & FLAGS_SHA1)) {
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/* SHA1 results are in big endian */
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/* SHA1 results are in big endian */
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for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
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for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
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- if (out)
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- hash[i] = be32_to_cpu(omap_sham_read(ctx->dd,
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- SHA_REG_DIGEST(i)));
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- else
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- omap_sham_write(ctx->dd, SHA_REG_DIGEST(i),
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- cpu_to_be32(hash[i]));
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+ hash[i] = be32_to_cpu(in[i]);
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} else {
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} else {
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/* MD5 results are in little endian */
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/* MD5 results are in little endian */
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for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
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for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
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- if (out)
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- hash[i] = le32_to_cpu(omap_sham_read(ctx->dd,
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- SHA_REG_DIGEST(i)));
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- else
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- omap_sham_write(ctx->dd, SHA_REG_DIGEST(i),
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- cpu_to_le32(hash[i]));
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+ hash[i] = le32_to_cpu(in[i]);
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}
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}
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}
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}
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-static int omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
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- int final, int dma)
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+static int omap_sham_hw_init(struct omap_sham_dev *dd)
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{
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{
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- struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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- u32 val = length << 5, mask;
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+ clk_enable(dd->iclk);
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- if (unlikely(!ctx->digcnt)) {
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+ if (!(dd->flags & FLAGS_INIT)) {
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+ omap_sham_write_mask(dd, SHA_REG_MASK,
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+ SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
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- clk_enable(dd->iclk);
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+ if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
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+ SHA_REG_SYSSTATUS_RESETDONE))
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+ return -ETIMEDOUT;
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- if (!(dd->flags & FLAGS_INIT)) {
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- omap_sham_write_mask(dd, SHA_REG_MASK,
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- SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
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+ dd->flags |= FLAGS_INIT;
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+ dd->err = 0;
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+ }
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- if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
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- SHA_REG_SYSSTATUS_RESETDONE))
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- return -ETIMEDOUT;
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+ return 0;
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+}
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- dd->flags |= FLAGS_INIT;
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- }
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- } else {
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+static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
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+ int final, int dma)
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+{
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+ struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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+ u32 val = length << 5, mask;
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+
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+ if (likely(ctx->digcnt))
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omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
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omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
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- }
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omap_sham_write_mask(dd, SHA_REG_MASK,
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omap_sham_write_mask(dd, SHA_REG_MASK,
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SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
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SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
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@@ -260,29 +281,26 @@ static int omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
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SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
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SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
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omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
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omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
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-
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- return 0;
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}
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}
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static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
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static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
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size_t length, int final)
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size_t length, int final)
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{
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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- int err, count, len32;
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+ int count, len32;
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const u32 *buffer = (const u32 *)buf;
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const u32 *buffer = (const u32 *)buf;
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dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
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dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
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ctx->digcnt, length, final);
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ctx->digcnt, length, final);
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- err = omap_sham_write_ctrl(dd, length, final, 0);
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- if (err)
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- return err;
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+ omap_sham_write_ctrl(dd, length, final, 0);
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+
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+ /* should be non-zero before next lines to disable clocks later */
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+ ctx->digcnt += length;
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if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
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if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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- ctx->digcnt += length;
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-
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if (final)
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if (final)
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ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
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ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
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@@ -298,16 +316,11 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
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size_t length, int final)
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size_t length, int final)
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{
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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- int err, len32;
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+ int len32;
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dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
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dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
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ctx->digcnt, length, final);
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ctx->digcnt, length, final);
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- /* flush cache entries related to our page */
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- if (dma_addr == ctx->dma_addr)
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- dma_sync_single_for_device(dd->dev, dma_addr, length,
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- DMA_TO_DEVICE);
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-
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
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omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
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@@ -317,9 +330,7 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
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omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
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omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
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dma_addr, 0, 0);
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dma_addr, 0, 0);
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- err = omap_sham_write_ctrl(dd, length, final, 1);
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- if (err)
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- return err;
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+ omap_sham_write_ctrl(dd, length, final, 1);
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ctx->digcnt += length;
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ctx->digcnt += length;
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@@ -371,15 +382,29 @@ static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
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return 0;
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return 0;
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}
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}
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+static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
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+ struct omap_sham_reqctx *ctx,
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+ size_t length, int final)
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+{
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+ ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
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+ DMA_TO_DEVICE);
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+ if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
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+ dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
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+ return -EINVAL;
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+ }
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+
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+ ctx->flags &= ~FLAGS_SG;
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+
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+ /* next call does not fail... so no unmap in the case of error */
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+ return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
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+}
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+
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static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
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static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
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{
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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unsigned int final;
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unsigned int final;
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size_t count;
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size_t count;
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- if (!ctx->total)
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- return 0;
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-
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omap_sham_append_sg(ctx);
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omap_sham_append_sg(ctx);
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final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
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final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
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@@ -390,30 +415,68 @@ static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
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if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
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if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
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count = ctx->bufcnt;
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count = ctx->bufcnt;
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ctx->bufcnt = 0;
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ctx->bufcnt = 0;
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- return omap_sham_xmit_dma(dd, ctx->dma_addr, count, final);
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+ return omap_sham_xmit_dma_map(dd, ctx, count, final);
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}
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}
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return 0;
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return 0;
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}
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}
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-static int omap_sham_update_dma_fast(struct omap_sham_dev *dd)
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+/* Start address alignment */
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+#define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
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+/* SHA1 block size alignment */
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+#define SG_SA(sg) (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE))
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+
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+static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
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{
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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- unsigned int length;
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+ unsigned int length, final, tail;
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+ struct scatterlist *sg;
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- ctx->flags |= FLAGS_FAST;
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+ if (!ctx->total)
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+ return 0;
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+
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+ if (ctx->bufcnt || ctx->offset)
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+ return omap_sham_update_dma_slow(dd);
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+
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+ dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
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+ ctx->digcnt, ctx->bufcnt, ctx->total);
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+
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+ sg = ctx->sg;
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- length = min(ctx->total, sg_dma_len(ctx->sg));
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- ctx->total = length;
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+ if (!SG_AA(sg))
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|
|
+ return omap_sham_update_dma_slow(dd);
|
|
|
|
+
|
|
|
|
+ if (!sg_is_last(sg) && !SG_SA(sg))
|
|
|
|
+ /* size is not SHA1_BLOCK_SIZE aligned */
|
|
|
|
+ return omap_sham_update_dma_slow(dd);
|
|
|
|
+
|
|
|
|
+ length = min(ctx->total, sg->length);
|
|
|
|
+
|
|
|
|
+ if (sg_is_last(sg)) {
|
|
|
|
+ if (!(ctx->flags & FLAGS_FINUP)) {
|
|
|
|
+ /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
|
|
|
|
+ tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
|
|
|
|
+ /* without finup() we need one block to close hash */
|
|
|
|
+ if (!tail)
|
|
|
|
+ tail = SHA1_MD5_BLOCK_SIZE;
|
|
|
|
+ length -= tail;
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
|
|
if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
|
|
if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
|
|
dev_err(dd->dev, "dma_map_sg error\n");
|
|
dev_err(dd->dev, "dma_map_sg error\n");
|
|
return -EINVAL;
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ ctx->flags |= FLAGS_SG;
|
|
|
|
+
|
|
ctx->total -= length;
|
|
ctx->total -= length;
|
|
|
|
+ ctx->offset = length; /* offset where to start slow */
|
|
|
|
|
|
- return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, 1);
|
|
|
|
|
|
+ final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
|
|
|
|
+
|
|
|
|
+ /* next call does not fail... so no unmap in the case of error */
|
|
|
|
+ return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
|
|
}
|
|
}
|
|
|
|
|
|
static int omap_sham_update_cpu(struct omap_sham_dev *dd)
|
|
static int omap_sham_update_cpu(struct omap_sham_dev *dd)
|
|
@@ -433,8 +496,17 @@ static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
|
|
|
|
|
|
omap_stop_dma(dd->dma_lch);
|
|
omap_stop_dma(dd->dma_lch);
|
|
- if (ctx->flags & FLAGS_FAST)
|
|
|
|
|
|
+ if (ctx->flags & FLAGS_SG) {
|
|
dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
|
|
dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
|
|
|
|
+ if (ctx->sg->length == ctx->offset) {
|
|
|
|
+ ctx->sg = sg_next(ctx->sg);
|
|
|
|
+ if (ctx->sg)
|
|
|
|
+ ctx->offset = 0;
|
|
|
|
+ }
|
|
|
|
+ } else {
|
|
|
|
+ dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
|
|
|
|
+ DMA_TO_DEVICE);
|
|
|
|
+ }
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
@@ -454,14 +526,7 @@ static void omap_sham_cleanup(struct ahash_request *req)
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
|
|
if (ctx->digcnt)
|
|
if (ctx->digcnt)
|
|
- clk_disable(dd->iclk);
|
|
|
|
-
|
|
|
|
- if (ctx->dma_addr)
|
|
|
|
- dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
|
|
|
|
- DMA_TO_DEVICE);
|
|
|
|
-
|
|
|
|
- if (ctx->buffer)
|
|
|
|
- free_page((unsigned long)ctx->buffer);
|
|
|
|
|
|
+ omap_sham_copy_ready_hash(req);
|
|
|
|
|
|
dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
|
|
dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
|
|
}
|
|
}
|
|
@@ -489,8 +554,6 @@ static int omap_sham_init(struct ahash_request *req)
|
|
|
|
|
|
ctx->flags = 0;
|
|
ctx->flags = 0;
|
|
|
|
|
|
- ctx->flags |= FLAGS_FIRST;
|
|
|
|
-
|
|
|
|
dev_dbg(dd->dev, "init: digest size: %d\n",
|
|
dev_dbg(dd->dev, "init: digest size: %d\n",
|
|
crypto_ahash_digestsize(tfm));
|
|
crypto_ahash_digestsize(tfm));
|
|
|
|
|
|
@@ -499,21 +562,7 @@ static int omap_sham_init(struct ahash_request *req)
|
|
|
|
|
|
ctx->bufcnt = 0;
|
|
ctx->bufcnt = 0;
|
|
ctx->digcnt = 0;
|
|
ctx->digcnt = 0;
|
|
-
|
|
|
|
- ctx->buflen = PAGE_SIZE;
|
|
|
|
- ctx->buffer = (void *)__get_free_page(
|
|
|
|
- (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
|
|
|
|
- GFP_KERNEL : GFP_ATOMIC);
|
|
|
|
- if (!ctx->buffer)
|
|
|
|
- return -ENOMEM;
|
|
|
|
-
|
|
|
|
- ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
|
|
|
|
- DMA_TO_DEVICE);
|
|
|
|
- if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
|
|
|
|
- dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
|
|
|
|
- free_page((unsigned long)ctx->buffer);
|
|
|
|
- return -EINVAL;
|
|
|
|
- }
|
|
|
|
|
|
+ ctx->buflen = BUFLEN;
|
|
|
|
|
|
if (tctx->flags & FLAGS_HMAC) {
|
|
if (tctx->flags & FLAGS_HMAC) {
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
@@ -538,10 +587,8 @@ static int omap_sham_update_req(struct omap_sham_dev *dd)
|
|
|
|
|
|
if (ctx->flags & FLAGS_CPU)
|
|
if (ctx->flags & FLAGS_CPU)
|
|
err = omap_sham_update_cpu(dd);
|
|
err = omap_sham_update_cpu(dd);
|
|
- else if (ctx->flags & FLAGS_FAST)
|
|
|
|
- err = omap_sham_update_dma_fast(dd);
|
|
|
|
else
|
|
else
|
|
- err = omap_sham_update_dma_slow(dd);
|
|
|
|
|
|
+ err = omap_sham_update_dma_start(dd);
|
|
|
|
|
|
/* wait for dma completion before can take more data */
|
|
/* wait for dma completion before can take more data */
|
|
dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
|
|
dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
|
|
@@ -560,15 +607,12 @@ static int omap_sham_final_req(struct omap_sham_dev *dd)
|
|
use_dma = 0;
|
|
use_dma = 0;
|
|
|
|
|
|
if (use_dma)
|
|
if (use_dma)
|
|
- err = omap_sham_xmit_dma(dd, ctx->dma_addr, ctx->bufcnt, 1);
|
|
|
|
|
|
+ err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
|
|
else
|
|
else
|
|
err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
|
|
err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
|
|
|
|
|
|
ctx->bufcnt = 0;
|
|
ctx->bufcnt = 0;
|
|
|
|
|
|
- if (err != -EINPROGRESS)
|
|
|
|
- omap_sham_cleanup(req);
|
|
|
|
-
|
|
|
|
dev_dbg(dd->dev, "final_req: err: %d\n", err);
|
|
dev_dbg(dd->dev, "final_req: err: %d\n", err);
|
|
|
|
|
|
return err;
|
|
return err;
|
|
@@ -576,6 +620,7 @@ static int omap_sham_final_req(struct omap_sham_dev *dd)
|
|
|
|
|
|
static int omap_sham_finish_req_hmac(struct ahash_request *req)
|
|
static int omap_sham_finish_req_hmac(struct ahash_request *req)
|
|
{
|
|
{
|
|
|
|
+ struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
int bs = crypto_shash_blocksize(bctx->shash);
|
|
int bs = crypto_shash_blocksize(bctx->shash);
|
|
@@ -590,48 +635,56 @@ static int omap_sham_finish_req_hmac(struct ahash_request *req)
|
|
|
|
|
|
return crypto_shash_init(&desc.shash) ?:
|
|
return crypto_shash_init(&desc.shash) ?:
|
|
crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
|
|
crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
|
|
- crypto_shash_finup(&desc.shash, req->result, ds, req->result);
|
|
|
|
|
|
+ crypto_shash_finup(&desc.shash, ctx->digest, ds, ctx->digest);
|
|
}
|
|
}
|
|
|
|
|
|
static void omap_sham_finish_req(struct ahash_request *req, int err)
|
|
static void omap_sham_finish_req(struct ahash_request *req, int err)
|
|
{
|
|
{
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
+ struct omap_sham_dev *dd = ctx->dd;
|
|
|
|
|
|
if (!err) {
|
|
if (!err) {
|
|
omap_sham_copy_hash(ctx->dd->req, 1);
|
|
omap_sham_copy_hash(ctx->dd->req, 1);
|
|
if (ctx->flags & FLAGS_HMAC)
|
|
if (ctx->flags & FLAGS_HMAC)
|
|
err = omap_sham_finish_req_hmac(req);
|
|
err = omap_sham_finish_req_hmac(req);
|
|
|
|
+ } else {
|
|
|
|
+ ctx->flags |= FLAGS_ERROR;
|
|
}
|
|
}
|
|
|
|
|
|
- if (ctx->flags & FLAGS_FINAL)
|
|
|
|
|
|
+ if ((ctx->flags & FLAGS_FINAL) || err)
|
|
omap_sham_cleanup(req);
|
|
omap_sham_cleanup(req);
|
|
|
|
|
|
- clear_bit(FLAGS_BUSY, &ctx->dd->flags);
|
|
|
|
|
|
+ clk_disable(dd->iclk);
|
|
|
|
+ dd->flags &= ~FLAGS_BUSY;
|
|
|
|
|
|
if (req->base.complete)
|
|
if (req->base.complete)
|
|
req->base.complete(&req->base, err);
|
|
req->base.complete(&req->base, err);
|
|
}
|
|
}
|
|
|
|
|
|
-static int omap_sham_handle_queue(struct omap_sham_dev *dd)
|
|
|
|
|
|
+static int omap_sham_handle_queue(struct omap_sham_dev *dd,
|
|
|
|
+ struct ahash_request *req)
|
|
{
|
|
{
|
|
struct crypto_async_request *async_req, *backlog;
|
|
struct crypto_async_request *async_req, *backlog;
|
|
struct omap_sham_reqctx *ctx;
|
|
struct omap_sham_reqctx *ctx;
|
|
- struct ahash_request *req, *prev_req;
|
|
|
|
|
|
+ struct ahash_request *prev_req;
|
|
unsigned long flags;
|
|
unsigned long flags;
|
|
- int err = 0;
|
|
|
|
-
|
|
|
|
- if (test_and_set_bit(FLAGS_BUSY, &dd->flags))
|
|
|
|
- return 0;
|
|
|
|
|
|
+ int err = 0, ret = 0;
|
|
|
|
|
|
spin_lock_irqsave(&dd->lock, flags);
|
|
spin_lock_irqsave(&dd->lock, flags);
|
|
|
|
+ if (req)
|
|
|
|
+ ret = ahash_enqueue_request(&dd->queue, req);
|
|
|
|
+ if (dd->flags & FLAGS_BUSY) {
|
|
|
|
+ spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
+ return ret;
|
|
|
|
+ }
|
|
backlog = crypto_get_backlog(&dd->queue);
|
|
backlog = crypto_get_backlog(&dd->queue);
|
|
async_req = crypto_dequeue_request(&dd->queue);
|
|
async_req = crypto_dequeue_request(&dd->queue);
|
|
- if (!async_req)
|
|
|
|
- clear_bit(FLAGS_BUSY, &dd->flags);
|
|
|
|
|
|
+ if (async_req)
|
|
|
|
+ dd->flags |= FLAGS_BUSY;
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
|
|
if (!async_req)
|
|
if (!async_req)
|
|
- return 0;
|
|
|
|
|
|
+ return ret;
|
|
|
|
|
|
if (backlog)
|
|
if (backlog)
|
|
backlog->complete(backlog, -EINPROGRESS);
|
|
backlog->complete(backlog, -EINPROGRESS);
|
|
@@ -646,7 +699,22 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd)
|
|
dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
|
|
dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
|
|
ctx->op, req->nbytes);
|
|
ctx->op, req->nbytes);
|
|
|
|
|
|
- if (req != prev_req && ctx->digcnt)
|
|
|
|
|
|
+
|
|
|
|
+ err = omap_sham_hw_init(dd);
|
|
|
|
+ if (err)
|
|
|
|
+ goto err1;
|
|
|
|
+
|
|
|
|
+ omap_set_dma_dest_params(dd->dma_lch, 0,
|
|
|
|
+ OMAP_DMA_AMODE_CONSTANT,
|
|
|
|
+ dd->phys_base + SHA_REG_DIN(0), 0, 16);
|
|
|
|
+
|
|
|
|
+ omap_set_dma_dest_burst_mode(dd->dma_lch,
|
|
|
|
+ OMAP_DMA_DATA_BURST_16);
|
|
|
|
+
|
|
|
|
+ omap_set_dma_src_burst_mode(dd->dma_lch,
|
|
|
|
+ OMAP_DMA_DATA_BURST_4);
|
|
|
|
+
|
|
|
|
+ if (ctx->digcnt)
|
|
/* request has changed - restore hash */
|
|
/* request has changed - restore hash */
|
|
omap_sham_copy_hash(req, 0);
|
|
omap_sham_copy_hash(req, 0);
|
|
|
|
|
|
@@ -658,7 +726,7 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd)
|
|
} else if (ctx->op == OP_FINAL) {
|
|
} else if (ctx->op == OP_FINAL) {
|
|
err = omap_sham_final_req(dd);
|
|
err = omap_sham_final_req(dd);
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+err1:
|
|
if (err != -EINPROGRESS) {
|
|
if (err != -EINPROGRESS) {
|
|
/* done_task will not finish it, so do it here */
|
|
/* done_task will not finish it, so do it here */
|
|
omap_sham_finish_req(req, err);
|
|
omap_sham_finish_req(req, err);
|
|
@@ -667,7 +735,7 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd)
|
|
|
|
|
|
dev_dbg(dd->dev, "exit, err: %d\n", err);
|
|
dev_dbg(dd->dev, "exit, err: %d\n", err);
|
|
|
|
|
|
- return err;
|
|
|
|
|
|
+ return ret;
|
|
}
|
|
}
|
|
|
|
|
|
static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
|
|
static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
|
|
@@ -675,18 +743,10 @@ static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
struct omap_sham_dev *dd = tctx->dd;
|
|
struct omap_sham_dev *dd = tctx->dd;
|
|
- unsigned long flags;
|
|
|
|
- int err;
|
|
|
|
|
|
|
|
ctx->op = op;
|
|
ctx->op = op;
|
|
|
|
|
|
- spin_lock_irqsave(&dd->lock, flags);
|
|
|
|
- err = ahash_enqueue_request(&dd->queue, req);
|
|
|
|
- spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
-
|
|
|
|
- omap_sham_handle_queue(dd);
|
|
|
|
-
|
|
|
|
- return err;
|
|
|
|
|
|
+ return omap_sham_handle_queue(dd, req);
|
|
}
|
|
}
|
|
|
|
|
|
static int omap_sham_update(struct ahash_request *req)
|
|
static int omap_sham_update(struct ahash_request *req)
|
|
@@ -709,21 +769,13 @@ static int omap_sham_update(struct ahash_request *req)
|
|
*/
|
|
*/
|
|
omap_sham_append_sg(ctx);
|
|
omap_sham_append_sg(ctx);
|
|
return 0;
|
|
return 0;
|
|
- } else if (ctx->bufcnt + ctx->total <= 64) {
|
|
|
|
|
|
+ } else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) {
|
|
|
|
+ /*
|
|
|
|
+ * faster to use CPU for short transfers
|
|
|
|
+ */
|
|
ctx->flags |= FLAGS_CPU;
|
|
ctx->flags |= FLAGS_CPU;
|
|
- } else if (!ctx->bufcnt && sg_is_last(ctx->sg)) {
|
|
|
|
- /* may be can use faster functions */
|
|
|
|
- int aligned = IS_ALIGNED((u32)ctx->sg->offset,
|
|
|
|
- sizeof(u32));
|
|
|
|
-
|
|
|
|
- if (aligned && (ctx->flags & FLAGS_FIRST))
|
|
|
|
- /* digest: first and final */
|
|
|
|
- ctx->flags |= FLAGS_FAST;
|
|
|
|
-
|
|
|
|
- ctx->flags &= ~FLAGS_FIRST;
|
|
|
|
}
|
|
}
|
|
- } else if (ctx->bufcnt + ctx->total <= ctx->buflen) {
|
|
|
|
- /* if not finaup -> not fast */
|
|
|
|
|
|
+ } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
|
|
omap_sham_append_sg(ctx);
|
|
omap_sham_append_sg(ctx);
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
@@ -761,12 +813,14 @@ static int omap_sham_final(struct ahash_request *req)
|
|
|
|
|
|
ctx->flags |= FLAGS_FINUP;
|
|
ctx->flags |= FLAGS_FINUP;
|
|
|
|
|
|
- /* OMAP HW accel works only with buffers >= 9 */
|
|
|
|
- /* HMAC is always >= 9 because of ipad */
|
|
|
|
- if ((ctx->digcnt + ctx->bufcnt) < 9)
|
|
|
|
- err = omap_sham_final_shash(req);
|
|
|
|
- else if (ctx->bufcnt)
|
|
|
|
- return omap_sham_enqueue(req, OP_FINAL);
|
|
|
|
|
|
+ if (!(ctx->flags & FLAGS_ERROR)) {
|
|
|
|
+ /* OMAP HW accel works only with buffers >= 9 */
|
|
|
|
+ /* HMAC is always >= 9 because of ipad */
|
|
|
|
+ if ((ctx->digcnt + ctx->bufcnt) < 9)
|
|
|
|
+ err = omap_sham_final_shash(req);
|
|
|
|
+ else if (ctx->bufcnt)
|
|
|
|
+ return omap_sham_enqueue(req, OP_FINAL);
|
|
|
|
+ }
|
|
|
|
|
|
omap_sham_cleanup(req);
|
|
omap_sham_cleanup(req);
|
|
|
|
|
|
@@ -836,6 +890,8 @@ static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
|
|
const char *alg_name = crypto_tfm_alg_name(tfm);
|
|
const char *alg_name = crypto_tfm_alg_name(tfm);
|
|
|
|
|
|
|
|
+ pr_info("enter\n");
|
|
|
|
+
|
|
/* Allocate a fallback and abort if it failed. */
|
|
/* Allocate a fallback and abort if it failed. */
|
|
tctx->fallback = crypto_alloc_shash(alg_name, 0,
|
|
tctx->fallback = crypto_alloc_shash(alg_name, 0,
|
|
CRYPTO_ALG_NEED_FALLBACK);
|
|
CRYPTO_ALG_NEED_FALLBACK);
|
|
@@ -846,7 +902,7 @@ static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
|
|
}
|
|
}
|
|
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
- sizeof(struct omap_sham_reqctx));
|
|
|
|
|
|
+ sizeof(struct omap_sham_reqctx) + BUFLEN);
|
|
|
|
|
|
if (alg_base) {
|
|
if (alg_base) {
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
@@ -932,7 +988,7 @@ static struct ahash_alg algs[] = {
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx),
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx),
|
|
- .cra_alignmask = 0,
|
|
|
|
|
|
+ .cra_alignmask = OMAP_ALIGN_MASK,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_sham_cra_init,
|
|
.cra_init = omap_sham_cra_init,
|
|
.cra_exit = omap_sham_cra_exit,
|
|
.cra_exit = omap_sham_cra_exit,
|
|
@@ -956,7 +1012,7 @@ static struct ahash_alg algs[] = {
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx) +
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx) +
|
|
sizeof(struct omap_sham_hmac_ctx),
|
|
sizeof(struct omap_sham_hmac_ctx),
|
|
- .cra_alignmask = 0,
|
|
|
|
|
|
+ .cra_alignmask = OMAP_ALIGN_MASK,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_sham_cra_sha1_init,
|
|
.cra_init = omap_sham_cra_sha1_init,
|
|
.cra_exit = omap_sham_cra_exit,
|
|
.cra_exit = omap_sham_cra_exit,
|
|
@@ -980,7 +1036,7 @@ static struct ahash_alg algs[] = {
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx) +
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx) +
|
|
sizeof(struct omap_sham_hmac_ctx),
|
|
sizeof(struct omap_sham_hmac_ctx),
|
|
- .cra_alignmask = 0,
|
|
|
|
|
|
+ .cra_alignmask = OMAP_ALIGN_MASK,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_init = omap_sham_cra_md5_init,
|
|
.cra_init = omap_sham_cra_md5_init,
|
|
.cra_exit = omap_sham_cra_exit,
|
|
.cra_exit = omap_sham_cra_exit,
|
|
@@ -993,7 +1049,7 @@ static void omap_sham_done_task(unsigned long data)
|
|
struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
|
|
struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
|
|
struct ahash_request *req = dd->req;
|
|
struct ahash_request *req = dd->req;
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
- int ready = 1;
|
|
|
|
|
|
+ int ready = 0, err = 0;
|
|
|
|
|
|
if (ctx->flags & FLAGS_OUTPUT_READY) {
|
|
if (ctx->flags & FLAGS_OUTPUT_READY) {
|
|
ctx->flags &= ~FLAGS_OUTPUT_READY;
|
|
ctx->flags &= ~FLAGS_OUTPUT_READY;
|
|
@@ -1003,15 +1059,18 @@ static void omap_sham_done_task(unsigned long data)
|
|
if (dd->flags & FLAGS_DMA_ACTIVE) {
|
|
if (dd->flags & FLAGS_DMA_ACTIVE) {
|
|
dd->flags &= ~FLAGS_DMA_ACTIVE;
|
|
dd->flags &= ~FLAGS_DMA_ACTIVE;
|
|
omap_sham_update_dma_stop(dd);
|
|
omap_sham_update_dma_stop(dd);
|
|
- omap_sham_update_dma_slow(dd);
|
|
|
|
|
|
+ if (!dd->err)
|
|
|
|
+ err = omap_sham_update_dma_start(dd);
|
|
}
|
|
}
|
|
|
|
|
|
- if (ready && !(dd->flags & FLAGS_DMA_ACTIVE)) {
|
|
|
|
- dev_dbg(dd->dev, "update done\n");
|
|
|
|
|
|
+ err = dd->err ? : err;
|
|
|
|
+
|
|
|
|
+ if (err != -EINPROGRESS && (ready || err)) {
|
|
|
|
+ dev_dbg(dd->dev, "update done: err: %d\n", err);
|
|
/* finish curent request */
|
|
/* finish curent request */
|
|
- omap_sham_finish_req(req, 0);
|
|
|
|
|
|
+ omap_sham_finish_req(req, err);
|
|
/* start new request */
|
|
/* start new request */
|
|
- omap_sham_handle_queue(dd);
|
|
|
|
|
|
+ omap_sham_handle_queue(dd, NULL);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
@@ -1019,7 +1078,7 @@ static void omap_sham_queue_task(unsigned long data)
|
|
{
|
|
{
|
|
struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
|
|
struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
|
|
|
|
|
|
- omap_sham_handle_queue(dd);
|
|
|
|
|
|
+ omap_sham_handle_queue(dd, NULL);
|
|
}
|
|
}
|
|
|
|
|
|
static irqreturn_t omap_sham_irq(int irq, void *dev_id)
|
|
static irqreturn_t omap_sham_irq(int irq, void *dev_id)
|
|
@@ -1041,6 +1100,7 @@ static irqreturn_t omap_sham_irq(int irq, void *dev_id)
|
|
omap_sham_read(dd, SHA_REG_CTRL);
|
|
omap_sham_read(dd, SHA_REG_CTRL);
|
|
|
|
|
|
ctx->flags |= FLAGS_OUTPUT_READY;
|
|
ctx->flags |= FLAGS_OUTPUT_READY;
|
|
|
|
+ dd->err = 0;
|
|
tasklet_schedule(&dd->done_task);
|
|
tasklet_schedule(&dd->done_task);
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
return IRQ_HANDLED;
|
|
@@ -1050,8 +1110,13 @@ static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
|
|
{
|
|
{
|
|
struct omap_sham_dev *dd = data;
|
|
struct omap_sham_dev *dd = data;
|
|
|
|
|
|
- if (likely(lch == dd->dma_lch))
|
|
|
|
- tasklet_schedule(&dd->done_task);
|
|
|
|
|
|
+ if (ch_status != OMAP_DMA_BLOCK_IRQ) {
|
|
|
|
+ pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
|
|
|
|
+ dd->err = -EIO;
|
|
|
|
+ dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ tasklet_schedule(&dd->done_task);
|
|
}
|
|
}
|
|
|
|
|
|
static int omap_sham_dma_init(struct omap_sham_dev *dd)
|
|
static int omap_sham_dma_init(struct omap_sham_dev *dd)
|
|
@@ -1066,15 +1131,6 @@ static int omap_sham_dma_init(struct omap_sham_dev *dd)
|
|
dev_err(dd->dev, "Unable to request DMA channel\n");
|
|
dev_err(dd->dev, "Unable to request DMA channel\n");
|
|
return err;
|
|
return err;
|
|
}
|
|
}
|
|
- omap_set_dma_dest_params(dd->dma_lch, 0,
|
|
|
|
- OMAP_DMA_AMODE_CONSTANT,
|
|
|
|
- dd->phys_base + SHA_REG_DIN(0), 0, 16);
|
|
|
|
-
|
|
|
|
- omap_set_dma_dest_burst_mode(dd->dma_lch,
|
|
|
|
- OMAP_DMA_DATA_BURST_16);
|
|
|
|
-
|
|
|
|
- omap_set_dma_src_burst_mode(dd->dma_lch,
|
|
|
|
- OMAP_DMA_DATA_BURST_4);
|
|
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|