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@@ -2512,31 +2512,32 @@ static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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return err;
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}
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-/* Assign Ram Buffer allocation to queue */
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-static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, u32 space)
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+static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
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{
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u32 end;
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- /* convert from K bytes to qwords used for hw register */
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- start *= 1024/8;
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- space *= 1024/8;
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- end = start + space - 1;
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+ start /= 8;
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+ len /= 8;
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+ end = start + len - 1;
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skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
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skge_write32(hw, RB_ADDR(q, RB_START), start);
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- skge_write32(hw, RB_ADDR(q, RB_END), end);
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skge_write32(hw, RB_ADDR(q, RB_WP), start);
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skge_write32(hw, RB_ADDR(q, RB_RP), start);
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+ skge_write32(hw, RB_ADDR(q, RB_END), end);
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if (q == Q_R1 || q == Q_R2) {
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- u32 tp = space - space/4;
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-
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/* Set thresholds on receive queue's */
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- skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
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- skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
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- } else if (hw->chip_id != CHIP_ID_GENESIS)
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- /* Genesis Tx Fifo is too small for normal store/forward */
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+ skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
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+ start + (2*len)/3);
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+ skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
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+ start + (len/3));
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+ } else {
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+ /* Enable store & forward on Tx queue's because
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+ * Tx FIFO is only 4K on Genesis and 1K on Yukon
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+ */
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skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
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+ }
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skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
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}
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@@ -2564,7 +2565,7 @@ static int skge_up(struct net_device *dev)
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struct skge_port *skge = netdev_priv(dev);
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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- u32 ramaddr, ramsize, rxspace;
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+ u32 chunk, ram_addr;
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size_t rx_size, tx_size;
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int err;
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@@ -2619,15 +2620,14 @@ static int skge_up(struct net_device *dev)
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spin_unlock_bh(&hw->phy_lock);
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/* Configure RAMbuffers */
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- ramsize = (hw->ram_size - hw->ram_offset) / hw->ports;
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- ramaddr = hw->ram_offset + port * ramsize;
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- rxspace = 8 + (2*(ramsize - 16))/3;
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-
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- skge_ramset(hw, rxqaddr[port], ramaddr, rxspace);
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- skge_ramset(hw, txqaddr[port], ramaddr + rxspace, ramsize - rxspace);
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+ chunk = hw->ram_size / ((hw->ports + 1)*2);
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+ ram_addr = hw->ram_offset + 2 * chunk * port;
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+ skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
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skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
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+
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BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
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+ skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
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skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
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/* Start receiver BMU */
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@@ -3591,12 +3591,15 @@ static int skge_reset(struct skge_hw *hw)
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if (hw->chip_id == CHIP_ID_GENESIS) {
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if (t8 == 3) {
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/* special case: 4 x 64k x 36, offset = 0x80000 */
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- hw->ram_size = 1024;
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- hw->ram_offset = 512;
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+ hw->ram_size = 0x100000;
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+ hw->ram_offset = 0x80000;
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} else
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hw->ram_size = t8 * 512;
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- } else /* Yukon */
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- hw->ram_size = t8 ? t8 * 4 : 128;
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+ }
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+ else if (t8 == 0)
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+ hw->ram_size = 0x20000;
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+ else
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+ hw->ram_size = t8 * 4096;
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hw->intr_mask = IS_HW_ERR;
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