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@@ -265,44 +265,12 @@ struct asic3_platform_data {
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#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
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/*********************************************
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- * The Onewire interface registers
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- *
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- * OWM_CMD
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- * OWM_DAT
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- * OWM_INTR
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- * OWM_INTEN
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- * OWM_CLKDIV
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+ * The Onewire interface (DS1WM) is handled
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+ * by the ds1wm driver.
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*
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*********************************************/
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-#define ASIC3_OWM_Base 0xC00
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-
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-#define ASIC3_OWM_CMD 0x00
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-#define ASIC3_OWM_DAT 0x04
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-#define ASIC3_OWM_INTR 0x08
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-#define ASIC3_OWM_INTEN 0x0C
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-#define ASIC3_OWM_CLKDIV 0x10
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-
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-#define ASIC3_OWM_CMD_ONEWR (1 << 0)
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-#define ASIC3_OWM_CMD_SRA (1 << 1)
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-#define ASIC3_OWM_CMD_DQO (1 << 2)
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-#define ASIC3_OWM_CMD_DQI (1 << 3)
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-
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-#define ASIC3_OWM_INTR_PD (1 << 0)
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-#define ASIC3_OWM_INTR_PDR (1 << 1)
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-#define ASIC3_OWM_INTR_TBE (1 << 2)
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-#define ASIC3_OWM_INTR_TEMP (1 << 3)
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-#define ASIC3_OWM_INTR_RBF (1 << 4)
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-
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-#define ASIC3_OWM_INTEN_EPD (1 << 0)
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-#define ASIC3_OWM_INTEN_IAS (1 << 1)
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-#define ASIC3_OWM_INTEN_ETBE (1 << 2)
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-#define ASIC3_OWM_INTEN_ETMT (1 << 3)
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-#define ASIC3_OWM_INTEN_ERBF (1 << 4)
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-
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-#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
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-#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
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-
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+#define ASIC3_OWM_BASE 0xC00
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/*****************************************************************************
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* The SD configuration registers are at a completely different location
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