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@@ -1800,6 +1800,9 @@ int r100_gpu_reset(struct radeon_device *rdev)
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void r100_set_common_regs(struct radeon_device *rdev)
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{
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+ struct drm_device *dev = rdev->ddev;
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+ bool force_dac2 = false;
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+
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/* set these so they don't interfere with anything */
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WREG32(RADEON_OV0_SCALE_CNTL, 0);
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WREG32(RADEON_SUBPIC_CNTL, 0);
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@@ -1808,6 +1811,68 @@ void r100_set_common_regs(struct radeon_device *rdev)
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WREG32(RADEON_DVI_I2C_CNTL_1, 0);
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WREG32(RADEON_CAP0_TRIG_CNTL, 0);
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WREG32(RADEON_CAP1_TRIG_CNTL, 0);
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+
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+ /* always set up dac2 on rn50 and some rv100 as lots
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+ * of servers seem to wire it up to a VGA port but
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+ * don't report it in the bios connector
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+ * table.
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+ */
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+ switch (dev->pdev->device) {
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+ /* RN50 */
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+ case 0x515e:
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+ case 0x5969:
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+ force_dac2 = true;
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+ break;
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+ /* RV100*/
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+ case 0x5159:
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+ case 0x515a:
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+ /* DELL triple head servers */
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+ if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
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+ ((dev->pdev->subsystem_device == 0x016c) ||
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+ (dev->pdev->subsystem_device == 0x016d) ||
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+ (dev->pdev->subsystem_device == 0x016e) ||
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+ (dev->pdev->subsystem_device == 0x016f) ||
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+ (dev->pdev->subsystem_device == 0x0170) ||
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+ (dev->pdev->subsystem_device == 0x017d) ||
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+ (dev->pdev->subsystem_device == 0x017e) ||
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+ (dev->pdev->subsystem_device == 0x0183) ||
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+ (dev->pdev->subsystem_device == 0x018a) ||
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+ (dev->pdev->subsystem_device == 0x019a)))
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+ force_dac2 = true;
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+ break;
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+ }
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+
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+ if (force_dac2) {
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+ u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
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+ u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
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+ u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
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+
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+ /* For CRT on DAC2, don't turn it on if BIOS didn't
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+ enable it, even it's detected.
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+ */
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+
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+ /* force it to crtc0 */
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+ dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
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+ dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
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+ disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
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+
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+ /* set up the TV DAC */
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+ tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
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+ RADEON_TV_DAC_STD_MASK |
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+ RADEON_TV_DAC_RDACPD |
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+ RADEON_TV_DAC_GDACPD |
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+ RADEON_TV_DAC_BDACPD |
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+ RADEON_TV_DAC_BGADJ_MASK |
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+ RADEON_TV_DAC_DACADJ_MASK);
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+ tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
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+ RADEON_TV_DAC_NHOLD |
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+ RADEON_TV_DAC_STD_PS2 |
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+ (0x58 << 16));
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+
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+ WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
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+ WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
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+ WREG32(RADEON_DAC_CNTL2, dac2_cntl);
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+ }
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}
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/*
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