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@@ -34,8 +34,8 @@
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#define CS2_BASE_ADDR 0xD0000000
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#define CS3_BASE_ADDR 0xD1000000
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#define CS4_BASE_ADDR 0xD2000000
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-#define CS5_BASE_ADDR 0xDD000000
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#define PCMCIA_MEM_BASE_ADDR 0xD4000000
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+#define CS5_BASE_ADDR 0xDD000000
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/* NAND, SDRAM, WEIM etc controllers */
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#define X_MEMC_BASE_ADDR 0xDF000000
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@@ -50,21 +50,21 @@
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#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
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/* fixed interrupt numbers */
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+#define MXC_INT_FIRI 9
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+#define MXC_INT_BMI 30
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+#define MXC_INT_EMMAENC 49
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+#define MXC_INT_EMMADEC 50
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+#define MXC_INT_USBWKUP 53
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+#define MXC_INT_USBDMA 54
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+#define MXC_INT_USBHOST 55
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+#define MXC_INT_USBFUNC 56
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+#define MXC_INT_USBMNP 57
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#define MXC_INT_USBCTRL 58
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#define MXC_INT_USBCTRL 58
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-#define MXC_INT_USBMNP 57
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-#define MXC_INT_USBFUNC 56
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-#define MXC_INT_USBHOST 55
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-#define MXC_INT_USBDMA 54
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-#define MXC_INT_USBWKUP 53
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-#define MXC_INT_EMMADEC 50
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-#define MXC_INT_EMMAENC 49
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-#define MXC_INT_BMI 30
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-#define MXC_INT_FIRI 9
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/* fixed DMA request numbers */
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-#define DMA_REQ_BMI_RX 29
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-#define DMA_REQ_BMI_TX 28
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#define DMA_REQ_FIRI_RX 4
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+#define DMA_REQ_BMI_TX 28
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+#define DMA_REQ_BMI_RX 29
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#endif /* __ASM_ARCH_MXC_MX21_H__ */
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