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@@ -0,0 +1,393 @@
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+/*
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+ *
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+ * Intel Management Engine Interface (Intel MEI) Linux driver
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+ * Copyright (c) 2003-2012, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ */
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+
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+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+
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+#include <linux/module.h>
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+#include <linux/moduleparam.h>
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+#include <linux/kernel.h>
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+#include <linux/device.h>
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+#include <linux/fs.h>
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+#include <linux/errno.h>
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+#include <linux/types.h>
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+#include <linux/fcntl.h>
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+#include <linux/aio.h>
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+#include <linux/pci.h>
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+#include <linux/poll.h>
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+#include <linux/init.h>
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+#include <linux/ioctl.h>
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+#include <linux/cdev.h>
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+#include <linux/sched.h>
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+#include <linux/uuid.h>
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+#include <linux/compat.h>
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+#include <linux/jiffies.h>
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+#include <linux/interrupt.h>
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+#include <linux/miscdevice.h>
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+
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+#include <linux/mei.h>
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+
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+#include "mei_dev.h"
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+#include "hw-me.h"
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+#include "client.h"
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+
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+/* AMT device is a singleton on the platform */
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+static struct pci_dev *mei_pdev;
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+
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+/* mei_pci_tbl - PCI Device ID Table */
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+static DEFINE_PCI_DEVICE_TABLE(mei_pci_tbl) = {
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT)},
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+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)},
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+
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+ /* required last entry */
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+ {0, }
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+};
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+
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+MODULE_DEVICE_TABLE(pci, mei_pci_tbl);
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+
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+static DEFINE_MUTEX(mei_mutex);
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+
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+
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+/**
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+ * mei_quirk_probe - probe for devices that doesn't valid ME interface
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+ * @pdev: PCI device structure
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+ * @ent: entry into pci_device_table
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+ *
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+ * returns true if ME Interface is valid, false otherwise
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+ */
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+static bool mei_quirk_probe(struct pci_dev *pdev,
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+ const struct pci_device_id *ent)
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+{
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+ u32 reg;
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+ if (ent->device == MEI_DEV_ID_PBG_1) {
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+ pci_read_config_dword(pdev, 0x48, ®);
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+ /* make sure that bit 9 is up and bit 10 is down */
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+ if ((reg & 0x600) == 0x200) {
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+ dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
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+ return false;
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+ }
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+ }
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+ return true;
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+}
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+/**
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+ * mei_probe - Device Initialization Routine
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+ *
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+ * @pdev: PCI device structure
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+ * @ent: entry in kcs_pci_tbl
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+ *
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+ * returns 0 on success, <0 on failure.
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+ */
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+static int mei_probe(struct pci_dev *pdev,
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+ const struct pci_device_id *ent)
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+{
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+ struct mei_device *dev;
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+ int err;
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+
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+ mutex_lock(&mei_mutex);
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+
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+ if (!mei_quirk_probe(pdev, ent)) {
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+ err = -ENODEV;
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+ goto end;
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+ }
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+
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+ if (mei_pdev) {
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+ err = -EEXIST;
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+ goto end;
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+ }
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+ /* enable pci dev */
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+ err = pci_enable_device(pdev);
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+ if (err) {
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+ dev_err(&pdev->dev, "failed to enable pci device.\n");
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+ goto end;
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+ }
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+ /* set PCI host mastering */
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+ pci_set_master(pdev);
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+ /* pci request regions for mei driver */
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+ err = pci_request_regions(pdev, KBUILD_MODNAME);
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+ if (err) {
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+ dev_err(&pdev->dev, "failed to get pci regions.\n");
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+ goto disable_device;
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+ }
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+ /* allocates and initializes the mei dev structure */
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+ dev = mei_device_init(pdev);
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+ if (!dev) {
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+ err = -ENOMEM;
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+ goto release_regions;
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+ }
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+ /* mapping IO device memory */
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+ dev->mem_addr = pci_iomap(pdev, 0, 0);
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+ if (!dev->mem_addr) {
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+ dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
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+ err = -ENOMEM;
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+ goto free_device;
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+ }
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+ pci_enable_msi(pdev);
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+
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+ /* request and enable interrupt */
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+ if (pci_dev_msi_enabled(pdev))
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+ err = request_threaded_irq(pdev->irq,
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+ NULL,
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+ mei_interrupt_thread_handler,
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+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
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+ else
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+ err = request_threaded_irq(pdev->irq,
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+ mei_interrupt_quick_handler,
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+ mei_interrupt_thread_handler,
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+ IRQF_SHARED, KBUILD_MODNAME, dev);
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+
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+ if (err) {
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+ dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
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+ pdev->irq);
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+ goto disable_msi;
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+ }
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+
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+ if (mei_hw_init(dev)) {
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+ dev_err(&pdev->dev, "init hw failure.\n");
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+ err = -ENODEV;
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+ goto release_irq;
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+ }
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+
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+ err = mei_register(&pdev->dev);
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+ if (err)
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+ goto release_irq;
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+
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+ mei_pdev = pdev;
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+ pci_set_drvdata(pdev, dev);
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+
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+
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+ schedule_delayed_work(&dev->timer_work, HZ);
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+
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+ mutex_unlock(&mei_mutex);
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+
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+ pr_debug("initialization successful.\n");
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+
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+ return 0;
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+
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+release_irq:
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+ mei_disable_interrupts(dev);
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+ flush_scheduled_work();
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+ free_irq(pdev->irq, dev);
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+disable_msi:
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+ pci_disable_msi(pdev);
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+ pci_iounmap(pdev, dev->mem_addr);
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+free_device:
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+ kfree(dev);
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+release_regions:
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+ pci_release_regions(pdev);
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+disable_device:
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+ pci_disable_device(pdev);
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+end:
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+ mutex_unlock(&mei_mutex);
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+ dev_err(&pdev->dev, "initialization failed.\n");
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+ return err;
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+}
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+
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+/**
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+ * mei_remove - Device Removal Routine
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+ *
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+ * @pdev: PCI device structure
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+ *
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+ * mei_remove is called by the PCI subsystem to alert the driver
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+ * that it should release a PCI device.
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+ */
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+static void mei_remove(struct pci_dev *pdev)
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+{
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+ struct mei_device *dev;
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+
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+ if (mei_pdev != pdev)
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+ return;
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+
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+ dev = pci_get_drvdata(pdev);
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+ if (!dev)
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+ return;
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+
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+ mutex_lock(&dev->device_lock);
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+
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+ cancel_delayed_work(&dev->timer_work);
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+
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+ mei_wd_stop(dev);
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+
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+ mei_pdev = NULL;
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+
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+ if (dev->iamthif_cl.state == MEI_FILE_CONNECTED) {
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+ dev->iamthif_cl.state = MEI_FILE_DISCONNECTING;
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+ mei_cl_disconnect(&dev->iamthif_cl);
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+ }
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+ if (dev->wd_cl.state == MEI_FILE_CONNECTED) {
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+ dev->wd_cl.state = MEI_FILE_DISCONNECTING;
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+ mei_cl_disconnect(&dev->wd_cl);
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+ }
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+
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+ /* Unregistering watchdog device */
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+ mei_watchdog_unregister(dev);
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+
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+ /* remove entry if already in list */
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+ dev_dbg(&pdev->dev, "list del iamthif and wd file list.\n");
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+
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+ if (dev->open_handle_count > 0)
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+ dev->open_handle_count--;
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+ mei_cl_unlink(&dev->wd_cl);
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+
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+ if (dev->open_handle_count > 0)
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+ dev->open_handle_count--;
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+ mei_cl_unlink(&dev->iamthif_cl);
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+
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+ dev->iamthif_current_cb = NULL;
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+ dev->me_clients_num = 0;
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+
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+ mutex_unlock(&dev->device_lock);
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+
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+ flush_scheduled_work();
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+
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+ /* disable interrupts */
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+ mei_disable_interrupts(dev);
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+
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+ free_irq(pdev->irq, dev);
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+ pci_disable_msi(pdev);
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+ pci_set_drvdata(pdev, NULL);
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+
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+ if (dev->mem_addr)
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+ pci_iounmap(pdev, dev->mem_addr);
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+
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+ kfree(dev);
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+
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+ pci_release_regions(pdev);
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+ pci_disable_device(pdev);
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+
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+ mei_deregister();
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+
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+}
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+#ifdef CONFIG_PM
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+static int mei_pci_suspend(struct device *device)
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+{
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+ struct pci_dev *pdev = to_pci_dev(device);
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+ struct mei_device *dev = pci_get_drvdata(pdev);
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+ int err;
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+
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+ if (!dev)
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+ return -ENODEV;
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+ mutex_lock(&dev->device_lock);
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+
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+ cancel_delayed_work(&dev->timer_work);
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+
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+ /* Stop watchdog if exists */
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+ err = mei_wd_stop(dev);
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+ /* Set new mei state */
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+ if (dev->dev_state == MEI_DEV_ENABLED ||
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+ dev->dev_state == MEI_DEV_RECOVERING_FROM_RESET) {
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+ dev->dev_state = MEI_DEV_POWER_DOWN;
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+ mei_reset(dev, 0);
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+ }
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+ mutex_unlock(&dev->device_lock);
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+
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+ free_irq(pdev->irq, dev);
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+ pci_disable_msi(pdev);
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+
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+ return err;
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+}
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+
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+static int mei_pci_resume(struct device *device)
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+{
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+ struct pci_dev *pdev = to_pci_dev(device);
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+ struct mei_device *dev;
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+ int err;
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+
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+ dev = pci_get_drvdata(pdev);
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+ if (!dev)
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+ return -ENODEV;
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+
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+ pci_enable_msi(pdev);
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+
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+ /* request and enable interrupt */
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+ if (pci_dev_msi_enabled(pdev))
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+ err = request_threaded_irq(pdev->irq,
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+ NULL,
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+ mei_interrupt_thread_handler,
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+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
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+ else
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+ err = request_threaded_irq(pdev->irq,
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+ mei_interrupt_quick_handler,
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+ mei_interrupt_thread_handler,
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+ IRQF_SHARED, KBUILD_MODNAME, dev);
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+
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+ if (err) {
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+ dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
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+ pdev->irq);
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+ return err;
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+ }
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+
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+ mutex_lock(&dev->device_lock);
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+ dev->dev_state = MEI_DEV_POWER_UP;
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+ mei_reset(dev, 1);
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+ mutex_unlock(&dev->device_lock);
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+
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+ /* Start timer if stopped in suspend */
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+ schedule_delayed_work(&dev->timer_work, HZ);
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+
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+ return err;
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+}
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+static SIMPLE_DEV_PM_OPS(mei_pm_ops, mei_pci_suspend, mei_pci_resume);
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+#define MEI_PM_OPS (&mei_pm_ops)
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+#else
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+#define MEI_PM_OPS NULL
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+#endif /* CONFIG_PM */
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+/*
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+ * PCI driver structure
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+ */
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+static struct pci_driver mei_driver = {
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+ .name = KBUILD_MODNAME,
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+ .id_table = mei_pci_tbl,
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+ .probe = mei_probe,
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+ .remove = mei_remove,
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+ .shutdown = mei_remove,
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+ .driver.pm = MEI_PM_OPS,
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+};
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+
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+module_pci_driver(mei_driver);
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+
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+MODULE_AUTHOR("Intel Corporation");
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+MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
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+MODULE_LICENSE("GPL v2");
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Tomas Winkler