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@@ -2409,6 +2409,39 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
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wm[3] *= 2;
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}
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+static void intel_print_wm_latency(struct drm_device *dev,
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+ const char *name,
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+ const uint16_t wm[5])
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+{
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+ int level, max_level;
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+
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+ /* how many WM levels are we expecting */
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+ if (IS_HASWELL(dev))
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+ max_level = 4;
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+ else if (INTEL_INFO(dev)->gen >= 6)
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+ max_level = 3;
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+ else
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+ max_level = 2;
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+
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+ for (level = 0; level <= max_level; level++) {
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+ unsigned int latency = wm[level];
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+
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+ if (latency == 0) {
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+ DRM_ERROR("%s WM%d latency not provided\n",
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+ name, level);
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+ continue;
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+ }
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+
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+ /* WM1+ latency values in 0.5us units */
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+ if (level > 0)
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+ latency *= 5;
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+
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+ DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
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+ name, level, wm[level],
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+ latency / 10, latency % 10);
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+ }
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+}
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+
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static void intel_setup_wm_latency(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -2422,6 +2455,10 @@ static void intel_setup_wm_latency(struct drm_device *dev)
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intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
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intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
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+
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+ intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
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+ intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
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+ intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
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}
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static void hsw_compute_wm_parameters(struct drm_device *dev,
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