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@@ -1027,32 +1027,6 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
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} s;
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};
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-/* ========================================================================= */
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-/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
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-/* ========================================================================= */
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
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-
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
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-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
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-
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-union uvh_rh_gam_mmioh_overlay_config_mmr_u {
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- unsigned long v;
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- struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
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- unsigned long rsvd_0_29: 30; /* */
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- unsigned long base : 16; /* RW */
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- unsigned long m_io : 6; /* RW */
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- unsigned long n_io : 4; /* RW */
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- unsigned long rsvd_56_62: 7; /* */
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- unsigned long enable : 1; /* RW */
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- } s;
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-};
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-
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/* ========================================================================= */
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/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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