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@@ -34,7 +34,8 @@
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static u8 twl4030_start_script_address = 0x2b;
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#define PWR_P1_SW_EVENTS 0x10
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-#define PWR_DEVOFF (1<<0)
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+#define PWR_DEVOFF (1 << 0)
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+#define SEQ_OFFSYNC (1 << 0)
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#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
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#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
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@@ -511,12 +512,27 @@ int twl4030_remove_script(u8 flags)
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return err;
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}
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+/*
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+ * In master mode, start the power off sequence.
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+ * After a successful execution, TWL shuts down the power to the SoC
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+ * and all peripherals connected to it.
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+ */
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+void twl4030_power_off(void)
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+{
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+ int err;
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+
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+ err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, PWR_DEVOFF,
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+ TWL4030_PM_MASTER_P1_SW_EVENTS);
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+ if (err)
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+ pr_err("TWL4030 Unable to power off\n");
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+}
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+
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void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
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{
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int err = 0;
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int i;
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struct twl4030_resconfig *resconfig;
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- u8 address = twl4030_start_script_address;
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+ u8 val, address = twl4030_start_script_address;
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err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
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TWL4030_PM_MASTER_KEY_CFG1,
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@@ -548,6 +564,28 @@ void __init twl4030_power_init(struct twl4030_power_data *twl4030_scripts)
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}
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}
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+ /* Board has to be wired properly to use this feature */
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+ if (twl4030_scripts->use_poweroff && !pm_power_off) {
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+ /* Default for SEQ_OFFSYNC is set, lets ensure this */
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+ err = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &val,
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+ TWL4030_PM_MASTER_CFG_P123_TRANSITION);
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+ if (err) {
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+ pr_warning("TWL4030 Unable to read registers\n");
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+
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+ } else if (!(val & SEQ_OFFSYNC)) {
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+ val |= SEQ_OFFSYNC;
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+ err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, val,
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+ TWL4030_PM_MASTER_CFG_P123_TRANSITION);
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+ if (err) {
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+ pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
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+ goto relock;
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+ }
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+ }
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+
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+ pm_power_off = twl4030_power_off;
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+ }
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+
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+relock:
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err = twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
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TWL4030_PM_MASTER_PROTECT_KEY);
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if (err)
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