serial: sh-sci: Move SCBRR calculation algo in to platform data.

This permits each port to select its own SCBRR calculation algorithm,
rather than having it all ifdef'ed in the header. There are presently
only 5 different variations that all parts fall under.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

arch/sh/kernel/cpu/sh2/setup-sh7619.c

@@ -64,18 +64,21 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xf8400000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 88, 88, 88, 88 },
 	}, {
 		.mapbase	= 0xf8410000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 92, 92, 92, 92 },
 	}, {
 		.mapbase	= 0xf8420000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 96, 96, 96, 96 },
 	}, {

arch/sh/kernel/cpu/sh2a/setup-mxg.c

@@ -212,6 +212,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xff804000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 220, 220, 220, 220 },
 	}, {

arch/sh/kernel/cpu/sh2a/setup-sh7201.c

@@ -182,48 +182,56 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xfffe8000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 180, 180, 180, 180 }
 	}, {
 		.mapbase	= 0xfffe8800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 184, 184, 184, 184 }
 	}, {
 		.mapbase	= 0xfffe9000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 188, 188, 188, 188 }
 	}, {
 		.mapbase	= 0xfffe9800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 192, 192, 192, 192 }
 	}, {
 		.mapbase	= 0xfffea000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 196, 196, 196, 196 }
 	}, {
 		.mapbase	= 0xfffea800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 200, 200, 200, 200 }
 	}, {
 		.mapbase	= 0xfffeb000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 204, 204, 204, 204 }
 	}, {
 		.mapbase	= 0xfffeb800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 208, 208, 208, 208 }
 	}, {

arch/sh/kernel/cpu/sh2a/setup-sh7203.c

@@ -178,24 +178,28 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xfffe8000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		=  { 192, 192, 192, 192 },
 	}, {
 		.mapbase	= 0xfffe8800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		=  { 196, 196, 196, 196 },
 	}, {
 		.mapbase	= 0xfffe9000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		=  { 200, 200, 200, 200 },
 	}, {
 		.mapbase	= 0xfffe9800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		=  { 204, 204, 204, 204 },
 	}, {

arch/sh/kernel/cpu/sh2a/setup-sh7206.c

@@ -138,24 +138,28 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xfffe8000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 240, 240, 240, 240 },
 	}, {
 		.mapbase	= 0xfffe8800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 244, 244, 244, 244 },
 	}, {
 		.mapbase	= 0xfffe9000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 248, 248, 248, 248 },
 	}, {
 		.mapbase	= 0xfffe9800,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 252, 252, 252, 252 },
 	}, {

arch/sh/kernel/cpu/sh3/setup-sh7705.c

@@ -73,12 +73,14 @@ static struct plat_sci_port sci_platform_data[] = {
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
 				  SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
+		.scbrr_algo_id	= SCBRR_ALGO_4,
 		.type		= PORT_SCIF,
 		.irqs		= { 56, 56, 56 },
 	}, {
 		.mapbase	= 0xa4400000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
+		.scbrr_algo_id	= SCBRR_ALGO_4,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 52, 52 },
 	}, {

arch/sh/kernel/cpu/sh3/setup-sh770x.c

@@ -111,6 +111,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xfffffe80,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TE | SCSCR_RE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCI,
 		.irqs		= { 23, 23, 23, 0 },
 	},
@@ -121,6 +122,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4000150,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TE | SCSCR_RE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 56, 56, 56, 56 },
 	},
@@ -131,6 +133,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4000140,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TE | SCSCR_RE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_IRDA,
 		.irqs		= { 52, 52, 52, 52 },
 	},

arch/sh/kernel/cpu/sh3/setup-sh7710.c

@@ -102,6 +102,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE |
 				  SCSCR_CKE1 | SCSCR_CKE0,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 52, 52, 52 },
 	}, {
@@ -109,6 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE |
 				  SCSCR_CKE1 | SCSCR_CKE0,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs           = { 56, 56, 56, 56 },
 	}, {

arch/sh/kernel/cpu/sh3/setup-sh7720.c

@@ -53,12 +53,14 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4430000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE,
+		.scbrr_algo_id	= SCBRR_ALGO_4,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 	}, {
 		.mapbase	= 0xa4438000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE,
+		.scbrr_algo_id	= SCBRR_ALGO_4,
 		.type		= PORT_SCIF,
 		.irqs           = { 81, 81, 81, 81 },
 	}, {

arch/sh/kernel/cpu/sh4/setup-sh4-202.c

@@ -20,6 +20,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe80000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 41, 43, 42 },
 	}, {

arch/sh/kernel/cpu/sh4/setup-sh7750.c

@@ -41,6 +41,7 @@ static struct plat_sci_port sci_platform_data = {
 	.flags		= UPF_BOOT_AUTOCONF,
 	.type		= PORT_SCI,
 	.scscr		= SCSCR_TE | SCSCR_RE,
+	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.irqs		= { 23, 23, 23, 0 },
 };
 
@@ -55,6 +56,7 @@ static struct plat_sci_port scif_platform_data = {
 	.mapbase	= 0xffe80000,
 	.flags		= UPF_BOOT_AUTOCONF,
 	.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE,
+	.scbrr_algo_id	= SCBRR_ALGO_2,
 	.type		= PORT_SCIF,
 	.irqs		= { 40, 40, 40, 40 },
 };

arch/sh/kernel/cpu/sh4/setup-sh7760.c

@@ -131,24 +131,28 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xfe600000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 53, 55, 54 },
 	}, {
 		.mapbase	= 0xfe610000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 72, 73, 75, 74 },
 	}, {
 		.mapbase	= 0xfe620000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 76, 77, 79, 78 },
 	}, {
 		.mapbase	= 0xfe480000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCI,
 		.irqs		= { 80, 81, 82, 0 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7343.c

@@ -270,6 +270,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 		.clk		= "scif0",
@@ -277,6 +278,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 81, 81, 81, 81 },
 		.clk		= "scif1",
@@ -284,6 +286,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe20000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 82, 82, 82, 82 },
 		.clk		= "scif2",
@@ -291,6 +294,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe30000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 83, 83, 83, 83 },
 		.clk		= "scif3",

arch/sh/kernel/cpu/sh4a/setup-sh7366.c

@@ -281,6 +281,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 		.clk		= "scif0",

arch/sh/kernel/cpu/sh4a/setup-sh7722.c

@@ -306,6 +306,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 80, 80, 80, 80 },
 		.clk		= "scif0",
@@ -313,6 +314,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 81, 81, 81, 81 },
 		.clk		= "scif1",
@@ -320,6 +322,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe20000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 82, 82, 82, 82 },
 		.clk		= "scif2",

arch/sh/kernel/cpu/sh4a/setup-sh7723.c

@@ -322,6 +322,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase        = 0xffe00000,
 		.flags          = UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type           = PORT_SCIF,
 		.irqs           = { 80, 80, 80, 80 },
 		.clk		= "scif0",
@@ -329,6 +330,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase        = 0xffe10000,
 		.flags          = UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type           = PORT_SCIF,
 		.irqs           = { 81, 81, 81, 81 },
 		.clk		= "scif1",
@@ -336,6 +338,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase        = 0xffe20000,
 		.flags          = UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type           = PORT_SCIF,
 		.irqs           = { 82, 82, 82, 82 },
 		.clk		= "scif2",
@@ -343,6 +346,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4e30000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_3,
 		.type		= PORT_SCIFA,
 		.irqs		= { 56, 56, 56, 56 },
 		.clk		= "scif3",
@@ -350,6 +354,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4e40000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_3,
 		.type		= PORT_SCIFA,
 		.irqs		= { 88, 88, 88, 88 },
 		.clk		= "scif4",
@@ -357,6 +362,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4e50000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_3,
 		.type		= PORT_SCIFA,
 		.irqs		= { 109, 109, 109, 109 },
 		.clk		= "scif5",

arch/sh/kernel/cpu/sh4a/setup-sh7724.c

@@ -29,6 +29,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase        = 0xffe00000,
 		.flags          = UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type           = PORT_SCIF,
 		.irqs           = { 80, 80, 80, 80 },
 		.clk		= "scif0",
@@ -36,6 +37,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase        = 0xffe10000,
 		.flags          = UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type           = PORT_SCIF,
 		.irqs           = { 81, 81, 81, 81 },
 		.clk		= "scif1",
@@ -43,6 +45,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase        = 0xffe20000,
 		.flags          = UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type           = PORT_SCIF,
 		.irqs           = { 82, 82, 82, 82 },
 		.clk		= "scif2",
@@ -50,6 +53,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4e30000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_3,
 		.type		= PORT_SCIFA,
 		.irqs		= { 56, 56, 56, 56 },
 		.clk		= "scif3",
@@ -57,6 +61,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4e40000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_3,
 		.type		= PORT_SCIFA,
 		.irqs		= { 88, 88, 88, 88 },
 		.clk		= "scif4",
@@ -64,6 +69,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xa4e50000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_3,
 		.type		= PORT_SCIFA,
 		.irqs		= { 109, 109, 109, 109 },
 		.clk		= "scif5",

arch/sh/kernel/cpu/sh4a/setup-sh7763.c

@@ -41,18 +41,21 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 40, 40, 40 },
 	}, {
 		.mapbase	= 0xffe08000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 76, 76, 76, 76 },
 	}, {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 104, 104, 104, 104 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7770.c

@@ -19,60 +19,70 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xff923000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 61, 61, 61, 61 },
 	}, {
 		.mapbase	= 0xff924000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 62, 62, 62, 62 },
 	}, {
 		.mapbase	= 0xff925000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 63, 63, 63, 63 },
 	}, {
 		.mapbase	= 0xff926000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 64, 64, 64, 64 },
 	}, {
 		.mapbase	= 0xff927000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 65, 65, 65, 65 },
 	}, {
 		.mapbase	= 0xff928000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 66, 66, 66, 66 },
 	}, {
 		.mapbase	= 0xff929000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 67, 67, 67, 67 },
 	}, {
 		.mapbase	= 0xff92a000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 68, 68, 68, 68 },
 	}, {
 		.mapbase	= 0xff92b000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 69, 69, 69, 69 },
 	}, {
 		.mapbase	= 0xff92c000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 70, 70, 70, 70 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7780.c

@@ -221,12 +221,14 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffe00000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 40, 40, 40 },
 	}, {
 		.mapbase	= 0xffe10000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 76, 76, 76, 76 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-sh7785.c

@@ -203,6 +203,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffea0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 40, 40, 40 },
 		.clk		= "scif_fck",
@@ -210,6 +211,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffeb0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 44, 44, 44, 44 },
 		.clk		= "scif_fck",
@@ -217,6 +219,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffec0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 60, 60, 60, 60 },
 		.clk		= "scif_fck",
@@ -224,6 +227,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffed0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 61, 61, 61, 61 },
 		.clk		= "scif_fck",
@@ -231,6 +235,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffee0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 62, 62, 62, 62 },
 		.clk		= "scif_fck",
@@ -238,6 +243,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffef0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 63, 63, 63, 63 },
 		.clk		= "scif_fck",

arch/sh/kernel/cpu/sh4a/setup-sh7786.c

@@ -28,6 +28,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffea0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 41, 43, 42 },
 	},
@@ -38,30 +39,35 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffeb0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 44, 44, 44, 44 },
 	}, {
 		.mapbase	= 0xffec0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 50, 50, 50, 50 },
 	}, {
 		.mapbase	= 0xffed0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 51, 51, 51, 51 },
 	}, {
 		.mapbase	= 0xffee0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 52, 52, 52 },
 	}, {
 		.mapbase	= 0xffef0000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+		.scbrr_algo_id	= SCBRR_ALGO_1,
 		.type		= PORT_SCIF,
 		.irqs		= { 53, 53, 53, 53 },
 	}, {

arch/sh/kernel/cpu/sh4a/setup-shx3.c

@@ -20,24 +20,28 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= 0xffc30000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 40, 41, 43, 42 },
 	}, {
 		.mapbase	= 0xffc40000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 44, 45, 47, 46 },
 	}, {
 		.mapbase	= 0xffc50000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 48, 49, 51, 50 },
 	}, {
 		.mapbase	= 0xffc60000,
 		.flags		= UPF_BOOT_AUTOCONF,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 52, 53, 55, 54 },
 	}, {

arch/sh/kernel/cpu/sh5/setup-sh5.c

@@ -21,6 +21,7 @@ static struct plat_sci_port sci_platform_data[] = {
 		.mapbase	= PHYS_PERIPHERAL_BLOCK + 0x01030000,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+		.scbrr_algo_id	= SCBRR_ALGO_2,
 		.type		= PORT_SCIF,
 		.irqs		= { 39, 40, 42, 0 },
 	}, {

drivers/serial/sh-sci.c

@@ -82,6 +82,9 @@ struct sci_port {
 	/* SCSCR initialization */
 	unsigned int		scscr;
 
+	/* SCBRR calculation algo */
+	unsigned int		scbrr_algo_id;
+
 #ifdef CONFIG_HAVE_CLK
 	/* Interface clock */
 	struct clk		*iclk;
@@ -928,6 +931,27 @@ static void sci_shutdown(struct uart_port *port)
 		s->disable(port);
 }
 
+static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
+				   unsigned long freq)
+{
+	switch (algo_id) {
+	case SCBRR_ALGO_1:
+		return ((freq + 16 * bps) / (16 * bps) - 1);
+	case SCBRR_ALGO_2:
+		return ((freq + 16 * bps) / (32 * bps) - 1);
+	case SCBRR_ALGO_3:
+		return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
+	case SCBRR_ALGO_4:
+		return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
+	case SCBRR_ALGO_5:
+		return (((freq * 1000 / 32) / bps) - 1);
+	}
+
+	/* Warn, but use a safe default */
+	WARN_ON(1);
+	return ((freq + 16 * bps) / (32 * bps) - 1);
+}
+
 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 			    struct ktermios *old)
 {
@@ -937,7 +961,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 
 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 	if (likely(baud))
-		t = SCBRR_VALUE(baud, port->uartclk);
+		t = sci_scbrr_calc(s->scbrr_algo_id, baud, port->uartclk);
 
 	do {
 		status = sci_in(port, SCxSR);
@@ -1108,7 +1132,6 @@ static void __devinit sci_init_single(struct platform_device *dev,
 	sci_port->type		= sci_port->port.type = p->type;
 
 	memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
-
 }
 
 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE

drivers/serial/sh-sci.h

@@ -713,59 +713,3 @@ static inline int sci_rxd_in(struct uart_port *port)
 	return 1;
 }
 #endif
-
-/*
- * Values for the BitRate Register (SCBRR)
- *
- * The values are actually divisors for a frequency which can
- * be internal to the SH3 (14.7456MHz) or derived from an external
- * clock source.  This driver assumes the internal clock is used;
- * to support using an external clock source, config options or
- * possibly command-line options would need to be added.
- *
- * Also, to support speeds below 2400 (why?) the lower 2 bits of
- * the SCSMR register would also need to be set to non-zero values.
- *
- * -- Greg Banks 27Feb2000
- *
- * Answer: The SCBRR register is only eight bits, and the value in
- * it gets larger with lower baud rates. At around 2400 (depending on
- * the peripherial module clock) you run out of bits. However the
- * lower two bits of SCSMR allow the module clock to be divided down,
- * scaling the value which is needed in SCBRR.
- *
- * -- Stuart Menefy - 23 May 2000
- *
- * I meant, why would anyone bother with bitrates below 2400.
- *
- * -- Greg Banks - 7Jul2000
- *
- * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
- * tape reader as a console!
- *
- * -- Mitch Davis - 15 Jul 2000
- */
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7785) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7786)
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
-      defined(CONFIG_CPU_SUBTYPE_SH7724)
-static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
-{
-	if (port->type == PORT_SCIF)
-		return (clk+16*bps)/(32*bps)-1;
-	else
-		return ((clk*2)+16*bps)/(16*bps)-1;
-}
-#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#else /* Generic SH */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
-#endif

include/linux/serial_sci.h

@@ -7,6 +7,14 @@
  * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
  */
 
+enum {
+	SCBRR_ALGO_1,		/* ((clk + 16 * bps) / (16 * bps) - 1) */
+	SCBRR_ALGO_2,		/* ((clk + 16 * bps) / (32 * bps) - 1) */
+	SCBRR_ALGO_3,		/* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
+	SCBRR_ALGO_4,		/* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
+	SCBRR_ALGO_5,		/* (((clk * 1000 / 32) / bps) - 1) */
+};
+
 #define SCSCR_TIE	(1 << 7)
 #define SCSCR_RIE	(1 << 6)
 #define SCSCR_TE	(1 << 5)
@@ -36,6 +44,7 @@ struct plat_sci_port {
 	upf_t		flags;			/* UPF_* flags */
 	char		*clk;			/* clock string */
 
+	unsigned int	scbrr_algo_id;		/* SCBRR calculation algo */
 	unsigned int	scscr;			/* SCSCR initialization */
 };