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@@ -31,6 +31,7 @@ static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
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static volatile long gsr_bits;
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static struct clk *ac97_clk;
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static struct clk *ac97conf_clk;
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+static int reset_gpio;
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/*
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* Beware PXA27x bugs:
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@@ -42,6 +43,45 @@ static struct clk *ac97conf_clk;
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* 1 jiffy timeout if interrupt never comes).
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*/
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+enum {
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+ RESETGPIO_FORCE_HIGH,
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+ RESETGPIO_FORCE_LOW,
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+ RESETGPIO_NORMAL_ALTFUNC
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+};
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+
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+/**
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+ * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
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+ * @mode: chosen action
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+ *
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+ * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
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+ * must be done to insure proper work of AC97 reset line. This function
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+ * computes the correct gpio_mode for further use by reset functions, and
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+ * applied the change through pxa_gpio_mode.
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+ */
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+static void set_resetgpio_mode(int resetgpio_action)
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+{
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+ int mode = 0;
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+
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+ if (reset_gpio)
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+ switch (resetgpio_action) {
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+ case RESETGPIO_NORMAL_ALTFUNC:
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+ if (reset_gpio == 113)
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+ mode = 113 | GPIO_OUT | GPIO_DFLT_LOW;
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+ if (reset_gpio == 95)
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+ mode = 95 | GPIO_ALT_FN_1_OUT;
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+ break;
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+ case RESETGPIO_FORCE_LOW:
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+ mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW;
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+ break;
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+ case RESETGPIO_FORCE_HIGH:
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+ mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH;
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+ break;
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+ };
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+
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+ if (mode)
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+ pxa_gpio_mode(mode);
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+}
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+
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unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
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{
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unsigned short val = -1;
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@@ -137,10 +177,10 @@ static inline void pxa_ac97_warm_pxa27x(void)
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/* warm reset broken on Bulverde,
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so manually keep AC97 reset high */
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- pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
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+ set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
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udelay(10);
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GCR |= GCR_WARM_RST;
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- pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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+ set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
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udelay(500);
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}
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@@ -308,8 +348,8 @@ int pxa2xx_ac97_hw_resume(void)
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pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
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}
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if (cpu_is_pxa27x()) {
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- /* Use GPIO 113 as AC97 Reset on Bulverde */
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- pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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+ /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
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+ set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
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}
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clk_enable(ac97_clk);
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return 0;
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@@ -320,6 +360,27 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
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int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
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{
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int ret;
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+ struct pxa2xx_ac97_platform_data *pdata = dev->dev.platform_data;
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+
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+ if (pdata) {
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+ switch (pdata->reset_gpio) {
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+ case 95:
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+ case 113:
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+ reset_gpio = pdata->reset_gpio;
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+ break;
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+ case 0:
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+ reset_gpio = 113;
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+ break;
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+ case -1:
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+ break;
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+ default:
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+ dev_err(dev, "Invalid reset GPIO %d\n",
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+ pdata->reset_gpio);
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+ }
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+ } else {
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+ if (cpu_is_pxa27x())
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+ reset_gpio = 113;
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+ }
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if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
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pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
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@@ -330,7 +391,7 @@ int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
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if (cpu_is_pxa27x()) {
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/* Use GPIO 113 as AC97 Reset on Bulverde */
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- pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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+ set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
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ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
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if (IS_ERR(ac97conf_clk)) {
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ret = PTR_ERR(ac97conf_clk);
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