Zynq is standard PMU with 2 interrupt per core. There is also access via register which is not used right now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
@@ -15,6 +15,13 @@
/ {
compatible = "xlnx,zynq-7000";
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 5 4>, <0 6 4>;
+ interrupt-parent = <&intc>;
+ reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+ };
+
amba {
compatible = "simple-bus";
#address-cells = <1>;