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@@ -0,0 +1,581 @@
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+/*****************************************************************************
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+* Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
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+*
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+* Unless you and Broadcom execute a separate written software license
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+* agreement governing use of this software, this software is licensed to you
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+* under the terms of the GNU General Public License version 2, available at
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+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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+*
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+* Notwithstanding the above, under no circumstances may you combine this
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+* software in any way with any other Broadcom software provided under a
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+* license other than the GPL, without Broadcom's express prior written
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+* consent.
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+*****************************************************************************/
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+
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+/* ---- Include Files ---------------------------------------------------- */
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+#include <linux/version.h>
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+#include <linux/module.h>
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+#include <linux/types.h>
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/string.h>
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+#include <linux/ioport.h>
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+#include <linux/device.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/platform_device.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/mtd/nand_ecc.h>
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+#include <linux/mtd/partitions.h>
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+
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+#include <asm/mach-types.h>
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+#include <asm/system.h>
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+
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+#include <mach/reg_nand.h>
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+#include <mach/reg_umi.h>
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+
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+#include "nand_bcm_umi.h"
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+
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+#include <mach/memory_settings.h>
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+
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+#define USE_DMA 1
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+#include <mach/dma.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/completion.h>
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+
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+/* ---- External Variable Declarations ----------------------------------- */
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+/* ---- External Function Prototypes ------------------------------------- */
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+/* ---- Public Variables ------------------------------------------------- */
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+/* ---- Private Constants and Types -------------------------------------- */
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+static const __devinitconst char gBanner[] = KERN_INFO \
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+ "BCM UMI MTD NAND Driver: 1.00\n";
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+
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+#ifdef CONFIG_MTD_PARTITIONS
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+const char *part_probes[] = { "cmdlinepart", NULL };
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+#endif
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+
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+#if NAND_ECC_BCH
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+static uint8_t scan_ff_pattern[] = { 0xff };
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+
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+static struct nand_bbt_descr largepage_bbt = {
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+ .options = 0,
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+ .offs = 0,
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+ .len = 1,
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+ .pattern = scan_ff_pattern
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+};
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+#endif
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+
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+/*
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+** Preallocate a buffer to avoid having to do this every dma operation.
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+** This is the size of the preallocated coherent DMA buffer.
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+*/
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+#if USE_DMA
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+#define DMA_MIN_BUFLEN 512
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+#define DMA_MAX_BUFLEN PAGE_SIZE
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+#define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \
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+ ((len) > DMA_MAX_BUFLEN))
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+
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+/*
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+ * The current NAND data space goes from 0x80001900 to 0x80001FFF,
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+ * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
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+ * size NAND flash. Need to break the DMA down to multiple 1Ks.
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+ *
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+ * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
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+ */
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+#define DMA_MAX_LEN 1024
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+
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+#else /* !USE_DMA */
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+#define DMA_MIN_BUFLEN 0
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+#define DMA_MAX_BUFLEN 0
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+#define USE_DIRECT_IO(len) 1
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+#endif
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+/* ---- Private Function Prototypes -------------------------------------- */
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+static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
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+static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
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+ int len);
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+
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+/* ---- Private Variables ------------------------------------------------ */
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+static struct mtd_info *board_mtd;
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+static void __iomem *bcm_umi_io_base;
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+static void *virtPtr;
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+static dma_addr_t physPtr;
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+static struct completion nand_comp;
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+
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+/* ---- Private Functions ------------------------------------------------ */
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+#if NAND_ECC_BCH
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+#include "bcm_umi_bch.c"
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+#else
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+#include "bcm_umi_hamming.c"
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+#endif
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+
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+#if USE_DMA
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+
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+/* Handler called when the DMA finishes. */
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+static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
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+{
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+ complete(&nand_comp);
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+}
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+
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+static int nand_dma_init(void)
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+{
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+ int rc;
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+
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+ rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
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+ nand_dma_handler, NULL);
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+ if (rc != 0) {
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+ printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
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+ return rc;
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+ }
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+
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+ virtPtr =
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+ dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
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+ if (virtPtr == NULL) {
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+ printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
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+ return -ENOMEM;
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+ }
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+
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+ return 0;
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+}
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+
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+static void nand_dma_term(void)
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+{
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+ if (virtPtr != NULL)
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+ dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
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+}
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+
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+static void nand_dma_read(void *buf, int len)
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+{
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+ int offset = 0;
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+ int tmp_len = 0;
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+ int len_left = len;
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+ DMA_Handle_t hndl;
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+
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+ if (virtPtr == NULL)
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+ panic("nand_dma_read: virtPtr == NULL\n");
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+
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+ if ((void *)physPtr == NULL)
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+ panic("nand_dma_read: physPtr == NULL\n");
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+
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+ hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
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+ if (hndl < 0) {
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+ printk(KERN_ERR
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+ "nand_dma_read: unable to allocate dma channel: %d\n",
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+ (int)hndl);
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+ panic("\n");
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+ }
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+
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+ while (len_left > 0) {
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+ if (len_left > DMA_MAX_LEN) {
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+ tmp_len = DMA_MAX_LEN;
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+ len_left -= DMA_MAX_LEN;
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+ } else {
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+ tmp_len = len_left;
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+ len_left = 0;
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+ }
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+
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+ init_completion(&nand_comp);
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+ dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
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+ physPtr + offset, tmp_len);
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+ wait_for_completion(&nand_comp);
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+
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+ offset += tmp_len;
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+ }
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+
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+ dma_free_channel(hndl);
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+
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+ if (buf != NULL)
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+ memcpy(buf, virtPtr, len);
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+}
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+
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+static void nand_dma_write(const void *buf, int len)
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+{
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+ int offset = 0;
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+ int tmp_len = 0;
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+ int len_left = len;
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+ DMA_Handle_t hndl;
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+
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+ if (buf == NULL)
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+ panic("nand_dma_write: buf == NULL\n");
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+
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+ if (virtPtr == NULL)
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+ panic("nand_dma_write: virtPtr == NULL\n");
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+
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+ if ((void *)physPtr == NULL)
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+ panic("nand_dma_write: physPtr == NULL\n");
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+
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+ memcpy(virtPtr, buf, len);
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+
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+
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+ hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
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+ if (hndl < 0) {
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+ printk(KERN_ERR
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+ "nand_dma_write: unable to allocate dma channel: %d\n",
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+ (int)hndl);
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+ panic("\n");
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+ }
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+
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+ while (len_left > 0) {
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+ if (len_left > DMA_MAX_LEN) {
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+ tmp_len = DMA_MAX_LEN;
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+ len_left -= DMA_MAX_LEN;
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+ } else {
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+ tmp_len = len_left;
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+ len_left = 0;
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+ }
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+
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+ init_completion(&nand_comp);
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+ dma_transfer_mem_to_mem(hndl, physPtr + offset,
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+ REG_NAND_DATA_PADDR, tmp_len);
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+ wait_for_completion(&nand_comp);
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+
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+ offset += tmp_len;
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+ }
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+
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+ dma_free_channel(hndl);
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+}
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+
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+#endif
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+
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+static int nand_dev_ready(struct mtd_info *mtd)
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+{
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+ return nand_bcm_umi_dev_ready();
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+}
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+
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+/****************************************************************************
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+*
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+* bcm_umi_nand_inithw
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+*
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+* This routine does the necessary hardware (board-specific)
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+* initializations. This includes setting up the timings, etc.
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+*
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+***************************************************************************/
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+int bcm_umi_nand_inithw(void)
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+{
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+ /* Configure nand timing parameters */
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+ REG_UMI_NAND_TCR &= ~0x7ffff;
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+ REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
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+
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+#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
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+ /* enable software control of CS */
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+ REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
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+#endif
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+
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+ /* keep NAND chip select asserted */
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+ REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
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+
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+ REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
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+ /* enable writes to flash */
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+ REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
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+
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+ writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
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+ nand_bcm_umi_wait_till_ready();
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+
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+#if NAND_ECC_BCH
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+ nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
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+#endif
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+
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+ return 0;
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+}
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+
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+/* Used to turn latch the proper register for access. */
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+static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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+ unsigned int ctrl)
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+{
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+ /* send command to hardware */
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+ struct nand_chip *chip = mtd->priv;
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+ if (ctrl & NAND_CTRL_CHANGE) {
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+ if (ctrl & NAND_CLE) {
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+ chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
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+ goto CMD;
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+ }
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+ if (ctrl & NAND_ALE) {
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+ chip->IO_ADDR_W =
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+ bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
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+ goto CMD;
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+ }
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+ chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
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+ }
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+
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+CMD:
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+ /* Send command to chip directly */
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+ if (cmd != NAND_CMD_NONE)
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+ writeb(cmd, chip->IO_ADDR_W);
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+}
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+
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+static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
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+ int len)
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+{
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+ if (USE_DIRECT_IO(len)) {
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+ /* Do it the old way if the buffer is small or too large.
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+ * Probably quicker than starting and checking dma. */
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+ int i;
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+ struct nand_chip *this = mtd->priv;
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+
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+ for (i = 0; i < len; i++)
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+ writeb(buf[i], this->IO_ADDR_W);
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+ }
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+#if USE_DMA
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+ else
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+ nand_dma_write(buf, len);
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+#endif
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+}
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+
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+static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
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+{
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+ if (USE_DIRECT_IO(len)) {
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+ int i;
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+ struct nand_chip *this = mtd->priv;
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+
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+ for (i = 0; i < len; i++)
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+ buf[i] = readb(this->IO_ADDR_R);
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+ }
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+#if USE_DMA
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+ else
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+ nand_dma_read(buf, len);
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+#endif
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+}
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+
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+static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
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+static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
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+ int len)
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+{
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+ /*
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+ * Try to readback page with ECC correction. This is necessary
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+ * for MLC parts which may have permanently stuck bits.
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+ */
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+ struct nand_chip *chip = mtd->priv;
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+ int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
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+ if (ret < 0)
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+ return -EFAULT;
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+ else {
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+ if (memcmp(readbackbuf, buf, len) == 0)
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+ return 0;
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+
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+ return -EFAULT;
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+ }
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+ return 0;
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+}
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+
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+static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
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+{
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+ struct nand_chip *this;
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+ struct resource *r;
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+ int err = 0;
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+
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+ printk(gBanner);
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+
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+ /* Allocate memory for MTD device structure and private data */
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+ board_mtd =
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+ kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
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+ GFP_KERNEL);
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+ if (!board_mtd) {
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+ printk(KERN_WARNING
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+ "Unable to allocate NAND MTD device structure.\n");
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+ return -ENOMEM;
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+ }
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+
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+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ if (!r)
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+ return -ENXIO;
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+
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+ /* map physical adress */
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+ bcm_umi_io_base = ioremap(r->start, r->end - r->start + 1);
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+
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+ if (!bcm_umi_io_base) {
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+ printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
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+ kfree(board_mtd);
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+ return -EIO;
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+ }
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+
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+ /* Get pointer to private data */
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+ this = (struct nand_chip *)(&board_mtd[1]);
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+
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+ /* Initialize structures */
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+ memset((char *)board_mtd, 0, sizeof(struct mtd_info));
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+ memset((char *)this, 0, sizeof(struct nand_chip));
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+
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+ /* Link the private data with the MTD structure */
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+ board_mtd->priv = this;
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+
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+ /* Initialize the NAND hardware. */
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+ if (bcm_umi_nand_inithw() < 0) {
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+ printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
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+ iounmap(bcm_umi_io_base);
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+ kfree(board_mtd);
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+ return -EIO;
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+ }
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+
|
|
|
+ /* Set address of NAND IO lines */
|
|
|
+ this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
|
|
|
+ this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
|
|
|
+
|
|
|
+ /* Set command delay time, see datasheet for correct value */
|
|
|
+ this->chip_delay = 0;
|
|
|
+ /* Assign the device ready function, if available */
|
|
|
+ this->dev_ready = nand_dev_ready;
|
|
|
+ this->options = 0;
|
|
|
+
|
|
|
+ this->write_buf = bcm_umi_nand_write_buf;
|
|
|
+ this->read_buf = bcm_umi_nand_read_buf;
|
|
|
+ this->verify_buf = bcm_umi_nand_verify_buf;
|
|
|
+
|
|
|
+ this->cmd_ctrl = bcm_umi_nand_hwcontrol;
|
|
|
+ this->ecc.mode = NAND_ECC_HW;
|
|
|
+ this->ecc.size = 512;
|
|
|
+ this->ecc.bytes = NAND_ECC_NUM_BYTES;
|
|
|
+#if NAND_ECC_BCH
|
|
|
+ this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
|
|
|
+ this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
|
|
|
+#else
|
|
|
+ this->ecc.correct = nand_correct_data512;
|
|
|
+ this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
|
|
|
+ this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
|
|
|
+#endif
|
|
|
+
|
|
|
+#if USE_DMA
|
|
|
+ err = nand_dma_init();
|
|
|
+ if (err != 0)
|
|
|
+ return err;
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* Figure out the size of the device that we have.
|
|
|
+ * We need to do this to figure out which ECC
|
|
|
+ * layout we'll be using.
|
|
|
+ */
|
|
|
+
|
|
|
+ err = nand_scan_ident(board_mtd, 1);
|
|
|
+ if (err) {
|
|
|
+ printk(KERN_ERR "nand_scan failed: %d\n", err);
|
|
|
+ iounmap(bcm_umi_io_base);
|
|
|
+ kfree(board_mtd);
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Now that we know the nand size, we can setup the ECC layout */
|
|
|
+
|
|
|
+ switch (board_mtd->writesize) { /* writesize is the pagesize */
|
|
|
+ case 4096:
|
|
|
+ this->ecc.layout = &nand_hw_eccoob_4096;
|
|
|
+ break;
|
|
|
+ case 2048:
|
|
|
+ this->ecc.layout = &nand_hw_eccoob_2048;
|
|
|
+ break;
|
|
|
+ case 512:
|
|
|
+ this->ecc.layout = &nand_hw_eccoob_512;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ {
|
|
|
+ printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
|
|
|
+ board_mtd->writesize);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+#if NAND_ECC_BCH
|
|
|
+ if (board_mtd->writesize > 512) {
|
|
|
+ if (this->options & NAND_USE_FLASH_BBT)
|
|
|
+ largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
|
|
|
+ this->badblock_pattern = &largepage_bbt;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* Now finish off the scan, now that ecc.layout has been initialized. */
|
|
|
+
|
|
|
+ err = nand_scan_tail(board_mtd);
|
|
|
+ if (err) {
|
|
|
+ printk(KERN_ERR "nand_scan failed: %d\n", err);
|
|
|
+ iounmap(bcm_umi_io_base);
|
|
|
+ kfree(board_mtd);
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Register the partitions */
|
|
|
+ {
|
|
|
+ int nr_partitions;
|
|
|
+ struct mtd_partition *partition_info;
|
|
|
+
|
|
|
+ board_mtd->name = "bcm_umi-nand";
|
|
|
+ nr_partitions =
|
|
|
+ parse_mtd_partitions(board_mtd, part_probes,
|
|
|
+ &partition_info, 0);
|
|
|
+
|
|
|
+ if (nr_partitions <= 0) {
|
|
|
+ printk(KERN_ERR "BCM UMI NAND: Too few partitions - %d\n",
|
|
|
+ nr_partitions);
|
|
|
+ iounmap(bcm_umi_io_base);
|
|
|
+ kfree(board_mtd);
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+ add_mtd_partitions(board_mtd, partition_info, nr_partitions);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Return happy */
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int bcm_umi_nand_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+#if USE_DMA
|
|
|
+ nand_dma_term();
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* Release resources, unregister device */
|
|
|
+ nand_release(board_mtd);
|
|
|
+
|
|
|
+ /* unmap physical adress */
|
|
|
+ iounmap(bcm_umi_io_base);
|
|
|
+
|
|
|
+ /* Free the MTD device structure */
|
|
|
+ kfree(board_mtd);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_PM
|
|
|
+static int bcm_umi_nand_suspend(struct platform_device *pdev,
|
|
|
+ pm_message_t state)
|
|
|
+{
|
|
|
+ printk(KERN_ERR "MTD NAND suspend is being called\n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int bcm_umi_nand_resume(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ printk(KERN_ERR "MTD NAND resume is being called\n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#else
|
|
|
+#define bcm_umi_nand_suspend NULL
|
|
|
+#define bcm_umi_nand_resume NULL
|
|
|
+#endif
|
|
|
+
|
|
|
+static struct platform_driver nand_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = "bcm-nand",
|
|
|
+ .owner = THIS_MODULE,
|
|
|
+ },
|
|
|
+ .probe = bcm_umi_nand_probe,
|
|
|
+ .remove = bcm_umi_nand_remove,
|
|
|
+ .suspend = bcm_umi_nand_suspend,
|
|
|
+ .resume = bcm_umi_nand_resume,
|
|
|
+};
|
|
|
+
|
|
|
+static int __init nand_init(void)
|
|
|
+{
|
|
|
+ return platform_driver_register(&nand_driver);
|
|
|
+}
|
|
|
+
|
|
|
+static void __exit nand_exit(void)
|
|
|
+{
|
|
|
+ platform_driver_unregister(&nand_driver);
|
|
|
+}
|
|
|
+
|
|
|
+module_init(nand_init);
|
|
|
+module_exit(nand_exit);
|
|
|
+
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+MODULE_AUTHOR("Broadcom");
|
|
|
+MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
|
Leo (Hao) Chen