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@@ -55,6 +55,19 @@ ENTRY(_start)
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andi r1, r1, ~2
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mts rmsr, r1
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+/*
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+ * Here is checking mechanism which check if Microblaze has msr instructions
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+ * We load msr and compare it with previous r1 value - if is the same,
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+ * msr instructions works if not - cpu don't have them.
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+ */
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+ or r8, r0, r0 /* 0 - I have msr instr, 1 - I don't have */
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+ or r12, r0, r0
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+ msrset r12, 0 /* set nothing - just read msr for test */
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+ cmpu r12, r12, r1
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+ beqi r12, 1f
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+ ori r8, r0, 1 /* I don't have msr */
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+1:
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+
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/* r7 may point to an FDT, or there may be one linked in.
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if it's in r7, we've got to save it away ASAP.
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We ensure r7 points to a valid FDT, just in case the bootloader
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@@ -209,8 +222,8 @@ start_here:
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* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
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* the function.
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*/
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- la r8, r0, machine_early_init
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- brald r15, r8
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+ la r9, r0, machine_early_init
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+ brald r15, r9
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nop
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#ifndef CONFIG_MMU
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