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@@ -5467,10 +5467,11 @@ static int cik_startup(struct radeon_device *rdev)
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return r;
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/* set up the compute queues */
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+ /* type-2 packets are deprecated on MEC, use type-3 instead */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
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CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
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- 0, 0xfffff, RADEON_CP_PACKET2);
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+ 0, 0xfffff, PACKET3(PACKET3_NOP, 0x3FFF));
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if (r)
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return r;
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ring->me = 1; /* first MEC */
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@@ -5478,10 +5479,11 @@ static int cik_startup(struct radeon_device *rdev)
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ring->queue = 0; /* first queue */
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ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
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+ /* type-2 packets are deprecated on MEC, use type-3 instead */
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
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CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,
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- 0, 0xffffffff, RADEON_CP_PACKET2);
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+ 0, 0xffffffff, PACKET3(PACKET3_NOP, 0x3FFF));
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if (r)
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return r;
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/* dGPU only have 1 MEC */
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