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@@ -55,81 +55,81 @@ static int debug;
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} while (0)
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static struct {u8 reg; u8 data;} cx24110_regdata[]=
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- /* Comments beginning with @ denote this value should
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- be the default */
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- {{0x09,0x01}, /* SoftResetAll */
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- {0x09,0x00}, /* release reset */
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- {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
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- {0x02,0x17}, /* middle byte " */
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- {0x03,0x29}, /* LSB " */
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- {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
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- {0x06,0xa5}, /* @ PLL 60MHz */
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- {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
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- {0x0a,0x00}, /* @ partial chip disables, do not set */
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- {0x0b,0x01}, /* set output clock in gapped mode, start signal low
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- active for first byte */
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- {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
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- {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
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- {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
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- to avoid starting the BER counter. Reset the
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- CRC test bit. Finite counting selected */
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- {0x15,0xff}, /* @ size of the limited time window for RS BER
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- estimation. It is <value>*256 RS blocks, this
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- gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
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- {0x16,0x00}, /* @ enable all RS output ports */
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- {0x17,0x04}, /* @ time window allowed for the RS to sync */
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- {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
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- for automatically */
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- /* leave the current code rate and normalization
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- registers as they are after reset... */
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- {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
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- only once */
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- {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
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- estimation. It is <value>*65536 channel bits, i.e.
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- approx. 38ms at 27.5MS/s, rate 3/4 */
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- {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
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- /* leave front-end AGC parameters at default values */
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- /* leave decimation AGC parameters at default values */
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- {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
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- {0x36,0xff}, /* clear all interrupt pending flags */
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- {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
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- {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
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- /* leave the equalizer parameters on their default values */
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- /* leave the final AGC parameters on their default values */
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- {0x41,0x00}, /* @ MSB of front-end derotator frequency */
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- {0x42,0x00}, /* @ middle bytes " */
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- {0x43,0x00}, /* @ LSB " */
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- /* leave the carrier tracking loop parameters on default */
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- /* leave the bit timing loop parameters at gefault */
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- {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
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- /* the cx24108 data sheet for symbol rates above 15MS/s */
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- {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
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- {0x61,0x95}, /* GPIO pins 1-4 have special function */
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- {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
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- {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
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- {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
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- {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
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- {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
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- {0x73,0x00}, /* @ disable several demod bypasses */
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- {0x74,0x00}, /* @ " */
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- {0x75,0x00} /* @ " */
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- /* the remaining registers are for SEC */
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+ /* Comments beginning with @ denote this value should
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+ be the default */
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+ {{0x09,0x01}, /* SoftResetAll */
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+ {0x09,0x00}, /* release reset */
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+ {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
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+ {0x02,0x17}, /* middle byte " */
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+ {0x03,0x29}, /* LSB " */
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+ {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
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+ {0x06,0xa5}, /* @ PLL 60MHz */
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+ {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
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+ {0x0a,0x00}, /* @ partial chip disables, do not set */
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+ {0x0b,0x01}, /* set output clock in gapped mode, start signal low
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+ active for first byte */
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+ {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
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+ {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
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+ {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
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+ to avoid starting the BER counter. Reset the
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+ CRC test bit. Finite counting selected */
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+ {0x15,0xff}, /* @ size of the limited time window for RS BER
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+ estimation. It is <value>*256 RS blocks, this
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+ gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
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+ {0x16,0x00}, /* @ enable all RS output ports */
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+ {0x17,0x04}, /* @ time window allowed for the RS to sync */
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+ {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
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+ for automatically */
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+ /* leave the current code rate and normalization
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+ registers as they are after reset... */
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+ {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
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+ only once */
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+ {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
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+ estimation. It is <value>*65536 channel bits, i.e.
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+ approx. 38ms at 27.5MS/s, rate 3/4 */
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+ {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
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+ /* leave front-end AGC parameters at default values */
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+ /* leave decimation AGC parameters at default values */
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+ {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
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+ {0x36,0xff}, /* clear all interrupt pending flags */
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+ {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
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+ {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
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+ /* leave the equalizer parameters on their default values */
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+ /* leave the final AGC parameters on their default values */
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+ {0x41,0x00}, /* @ MSB of front-end derotator frequency */
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+ {0x42,0x00}, /* @ middle bytes " */
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+ {0x43,0x00}, /* @ LSB " */
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+ /* leave the carrier tracking loop parameters on default */
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+ /* leave the bit timing loop parameters at gefault */
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+ {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
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+ /* the cx24108 data sheet for symbol rates above 15MS/s */
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+ {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
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+ {0x61,0x95}, /* GPIO pins 1-4 have special function */
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+ {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
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+ {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
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+ {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
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+ {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
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+ {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
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+ {0x73,0x00}, /* @ disable several demod bypasses */
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+ {0x74,0x00}, /* @ " */
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+ {0x75,0x00} /* @ " */
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+ /* the remaining registers are for SEC */
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};
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static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
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{
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- u8 buf [] = { reg, data };
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+ u8 buf [] = { reg, data };
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struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
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int err;
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- if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
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+ if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
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dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
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" data == 0x%02x)\n", __FUNCTION__, err, reg, data);
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return -EREMOTEIO;
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}
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- return 0;
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+ return 0;
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}
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static int cx24110_readreg (struct cx24110_state* state, u8 reg)
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@@ -153,27 +153,27 @@ static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inver
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switch (inversion) {
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case INVERSION_OFF:
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- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
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- /* AcqSpectrInvDis on. No idea why someone should want this */
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- cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
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- /* Initial value 0 at start of acq */
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- cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
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- /* current value 0 */
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- /* The cx24110 manual tells us this reg is read-only.
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- But what the heck... set it ayways */
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- break;
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+ cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
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+ /* AcqSpectrInvDis on. No idea why someone should want this */
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+ cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
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+ /* Initial value 0 at start of acq */
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+ cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
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+ /* current value 0 */
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+ /* The cx24110 manual tells us this reg is read-only.
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+ But what the heck... set it ayways */
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+ break;
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case INVERSION_ON:
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- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
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- /* AcqSpectrInvDis on. No idea why someone should want this */
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- cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
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- /* Initial value 1 at start of acq */
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- cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
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- /* current value 1 */
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- break;
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+ cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
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+ /* AcqSpectrInvDis on. No idea why someone should want this */
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+ cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
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+ /* Initial value 1 at start of acq */
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+ cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
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+ /* current value 1 */
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+ break;
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case INVERSION_AUTO:
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- cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
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- /* AcqSpectrInvDis off. Leave initial & current states as is */
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- break;
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+ cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
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+ /* AcqSpectrInvDis off. Leave initial & current states as is */
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+ break;
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default:
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return -EINVAL;
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}
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@@ -185,18 +185,18 @@ static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
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{
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/* fixme (low): error handling */
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- static const int rate[]={-1,1,2,3,5,7,-1};
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- static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
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- static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
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+ static const int rate[]={-1,1,2,3,5,7,-1};
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+ static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
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+ static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
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- /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
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- searches all enabled viterbi rates, and can handle non-standard
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- rates as well. */
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+ /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
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+ searches all enabled viterbi rates, and can handle non-standard
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+ rates as well. */
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- if (fec>FEC_AUTO)
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- fec=FEC_AUTO;
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+ if (fec>FEC_AUTO)
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+ fec=FEC_AUTO;
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- if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
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+ if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
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cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf);
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/* clear AcqVitDis bit */
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cx24110_writereg(state,0x18,0xae);
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@@ -208,7 +208,7 @@ static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
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cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06);
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/* set the puncture registers for code rate 3/4 */
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return 0;
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- } else {
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+ } else {
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cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20);
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/* set AcqVitDis bit */
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if(rate[fec]>0) {
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@@ -219,10 +219,10 @@ static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
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cx24110_writereg(state,0x1a,g1[fec]);
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cx24110_writereg(state,0x1b,g2[fec]);
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/* not sure if this is the right way: I always used AutoAcq mode */
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- } else
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+ } else
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return -EOPNOTSUPP;
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/* fixme (low): which is the correct return code? */
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- };
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+ };
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return 0;
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}
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@@ -245,72 +245,72 @@ static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
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static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
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{
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/* fixme (low): add error handling */
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- u32 ratio;
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- u32 tmp, fclk, BDRI;
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+ u32 ratio;
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+ u32 tmp, fclk, BDRI;
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- static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
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- int i;
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+ static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
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+ int i;
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dprintk("cx24110 debug: entering %s(%d)\n",__FUNCTION__,srate);
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- if (srate>90999000UL/2)
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- srate=90999000UL/2;
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- if (srate<500000)
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- srate=500000;
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+ if (srate>90999000UL/2)
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+ srate=90999000UL/2;
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+ if (srate<500000)
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+ srate=500000;
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- for(i=0;(i<sizeof(bands)/sizeof(bands[0]))&&(srate>bands[i]);i++)
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+ for(i=0;(i<sizeof(bands)/sizeof(bands[0]))&&(srate>bands[i]);i++)
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;
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- /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
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- and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
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- R06[3:0] PLLphaseDetGain */
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- tmp=cx24110_readreg(state,0x07)&0xfc;
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- if(srate<90999000UL/4) { /* sample rate 45MHz*/
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+ /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
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+ and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
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+ R06[3:0] PLLphaseDetGain */
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+ tmp=cx24110_readreg(state,0x07)&0xfc;
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+ if(srate<90999000UL/4) { /* sample rate 45MHz*/
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cx24110_writereg(state,0x07,tmp);
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cx24110_writereg(state,0x06,0x78);
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fclk=90999000UL/2;
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- } else if(srate<60666000UL/2) { /* sample rate 60MHz */
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+ } else if(srate<60666000UL/2) { /* sample rate 60MHz */
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cx24110_writereg(state,0x07,tmp|0x1);
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cx24110_writereg(state,0x06,0xa5);
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fclk=60666000UL;
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- } else if(srate<80888000UL/2) { /* sample rate 80MHz */
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+ } else if(srate<80888000UL/2) { /* sample rate 80MHz */
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cx24110_writereg(state,0x07,tmp|0x2);
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cx24110_writereg(state,0x06,0x87);
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fclk=80888000UL;
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- } else { /* sample rate 90MHz */
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+ } else { /* sample rate 90MHz */
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cx24110_writereg(state,0x07,tmp|0x3);
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cx24110_writereg(state,0x06,0x78);
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fclk=90999000UL;
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- };
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- dprintk("cx24110 debug: fclk %d Hz\n",fclk);
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- /* we need to divide two integers with approx. 27 bits in 32 bit
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- arithmetic giving a 25 bit result */
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- /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
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- also the most complex divisor. Hence, the dividend has,
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- assuming 32bit unsigned arithmetic, 6 clear bits on top, the
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- divisor 2 unused bits at the bottom. Also, the quotient is
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- always less than 1/2. Borrowed from VES1893.c, of course */
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+ };
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+ dprintk("cx24110 debug: fclk %d Hz\n",fclk);
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+ /* we need to divide two integers with approx. 27 bits in 32 bit
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+ arithmetic giving a 25 bit result */
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+ /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
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+ also the most complex divisor. Hence, the dividend has,
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+ assuming 32bit unsigned arithmetic, 6 clear bits on top, the
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+ divisor 2 unused bits at the bottom. Also, the quotient is
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+ always less than 1/2. Borrowed from VES1893.c, of course */
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- tmp=srate<<6;
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- BDRI=fclk>>2;
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- ratio=(tmp/BDRI);
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+ tmp=srate<<6;
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+ BDRI=fclk>>2;
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+ ratio=(tmp/BDRI);
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- tmp=(tmp%BDRI)<<8;
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- ratio=(ratio<<8)+(tmp/BDRI);
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+ tmp=(tmp%BDRI)<<8;
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+ ratio=(ratio<<8)+(tmp/BDRI);
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- tmp=(tmp%BDRI)<<8;
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- ratio=(ratio<<8)+(tmp/BDRI);
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+ tmp=(tmp%BDRI)<<8;
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+ ratio=(ratio<<8)+(tmp/BDRI);
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- tmp=(tmp%BDRI)<<1;
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- ratio=(ratio<<1)+(tmp/BDRI);
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+ tmp=(tmp%BDRI)<<1;
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+ ratio=(ratio<<1)+(tmp/BDRI);
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- dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
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- dprintk("fclk = %d\n", fclk);
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- dprintk("ratio= %08x\n", ratio);
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+ dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
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+ dprintk("fclk = %d\n", fclk);
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+ dprintk("ratio= %08x\n", ratio);
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- cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
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- cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
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- cx24110_writereg(state, 0x3, (ratio)&0xff);
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+ cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
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+ cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
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+ cx24110_writereg(state, 0x3, (ratio)&0xff);
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- return 0;
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+ return 0;
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}
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@@ -324,48 +324,48 @@ int cx24110_pll_write (struct dvb_frontend* fe, u32 data)
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dprintk("cx24110 debug: cx24108_write(%8.8x)\n",data);
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- cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
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- cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
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+ cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
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+ cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
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- /* if the auto tuner writer is still busy, clear it out */
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- while (cx24110_readreg(state,0x6d)&0x80)
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+ /* if the auto tuner writer is still busy, clear it out */
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+ while (cx24110_readreg(state,0x6d)&0x80)
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cx24110_writereg(state,0x72,0);
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- /* write the topmost 8 bits */
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- cx24110_writereg(state,0x72,(data>>24)&0xff);
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+ /* write the topmost 8 bits */
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+ cx24110_writereg(state,0x72,(data>>24)&0xff);
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|
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- /* wait for the send to be completed */
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- while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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+ /* wait for the send to be completed */
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+ while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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|
;
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|
|
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|
- /* send another 8 bytes */
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|
- cx24110_writereg(state,0x72,(data>>16)&0xff);
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- while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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|
+ /* send another 8 bytes */
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|
|
+ cx24110_writereg(state,0x72,(data>>16)&0xff);
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|
|
+ while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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|
|
;
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|
|
|
|
- /* and the topmost 5 bits of this byte */
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|
|
- cx24110_writereg(state,0x72,(data>>8)&0xff);
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|
|
- while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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|
|
+ /* and the topmost 5 bits of this byte */
|
|
|
+ cx24110_writereg(state,0x72,(data>>8)&0xff);
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|
|
+ while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
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|
|
;
|
|
|
|
|
|
- /* now strobe the enable line once */
|
|
|
- cx24110_writereg(state,0x6d,0x32);
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|
|
- cx24110_writereg(state,0x6d,0x30);
|
|
|
+ /* now strobe the enable line once */
|
|
|
+ cx24110_writereg(state,0x6d,0x32);
|
|
|
+ cx24110_writereg(state,0x6d,0x30);
|
|
|
|
|
|
- return 0;
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
static int cx24110_initfe(struct dvb_frontend* fe)
|
|
|
{
|
|
|
struct cx24110_state *state = fe->demodulator_priv;
|
|
|
/* fixme (low): error handling */
|
|
|
- int i;
|
|
|
+ int i;
|
|
|
|
|
|
dprintk("%s: init chip\n", __FUNCTION__);
|
|
|
|
|
|
- for(i=0;i<sizeof(cx24110_regdata)/sizeof(cx24110_regdata[0]);i++) {
|
|
|
+ for(i=0;i<sizeof(cx24110_regdata)/sizeof(cx24110_regdata[0]);i++) {
|
|
|
cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
|
|
|
- };
|
|
|
+ };
|
|
|
|
|
|
if (state->config->pll_init) state->config->pll_init(fe);
|
|
|
|