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@@ -27,6 +27,7 @@
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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+#include <asm/sections.h>
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int split_tlb;
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int dcache_stride;
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@@ -207,6 +208,9 @@ parisc_cache_init(void)
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/* "New and Improved" version from Jim Hull
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* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
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+ * The following CAFL_STRIDE is an optimized version, see
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+ * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
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+ * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
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*/
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#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
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dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
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@@ -339,17 +343,15 @@ int parisc_cache_flush_threshold = FLUSH_THRESHOLD;
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void parisc_setup_cache_timing(void)
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{
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unsigned long rangetime, alltime;
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- extern char _text; /* start of kernel code, defined by linker */
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- extern char _end; /* end of BSS, defined by linker */
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unsigned long size;
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alltime = mfctl(16);
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flush_data_cache();
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alltime = mfctl(16) - alltime;
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- size = (unsigned long)(&_end - _text);
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+ size = (unsigned long)(_end - _text);
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rangetime = mfctl(16);
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- flush_kernel_dcache_range((unsigned long)&_text, size);
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+ flush_kernel_dcache_range((unsigned long)_text, size);
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rangetime = mfctl(16) - rangetime;
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printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
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