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@@ -2902,7 +2902,18 @@ static void valleyview_enable_rps(struct drm_device *dev)
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GEN7_RC_CTL_TO_MODE);
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valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
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- dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
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+ switch ((val >> 6) & 3) {
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+ case 0:
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+ case 1:
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+ dev_priv->mem_freq = 800;
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+ break;
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+ case 2:
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+ dev_priv->mem_freq = 1066;
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+ break;
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+ case 3:
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+ dev_priv->mem_freq = 1333;
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+ break;
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+ }
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DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
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DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
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