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@@ -0,0 +1,1171 @@
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+/*
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+ * Clock tree for CSR SiRFprimaII
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+ *
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+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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+ *
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+ * Licensed under GPLv2 or later.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/bitops.h>
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+#include <linux/io.h>
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+#include <linux/clk.h>
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+#include <linux/clkdev.h>
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+#include <linux/clk-provider.h>
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+#include <linux/of_address.h>
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+#include <linux/syscore_ops.h>
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+
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+#define SIRFSOC_CLKC_CLK_EN0 0x0000
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+#define SIRFSOC_CLKC_CLK_EN1 0x0004
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+#define SIRFSOC_CLKC_REF_CFG 0x0014
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+#define SIRFSOC_CLKC_CPU_CFG 0x0018
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+#define SIRFSOC_CLKC_MEM_CFG 0x001c
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+#define SIRFSOC_CLKC_SYS_CFG 0x0020
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+#define SIRFSOC_CLKC_IO_CFG 0x0024
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+#define SIRFSOC_CLKC_DSP_CFG 0x0028
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+#define SIRFSOC_CLKC_GFX_CFG 0x002c
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+#define SIRFSOC_CLKC_MM_CFG 0x0030
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+#define SIRFSOC_CLKC_LCD_CFG 0x0034
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+#define SIRFSOC_CLKC_MMC_CFG 0x0038
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+#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
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+#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
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+#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
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+#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
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+#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
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+#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
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+#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
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+#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
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+#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
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+#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
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+#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
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+#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
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+#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
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+
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+static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
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+
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+#define KHZ 1000
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+#define MHZ (KHZ * KHZ)
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+
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+/*
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+ * SiRFprimaII clock controller
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+ * - 2 oscillators: osc-26MHz, rtc-32.768KHz
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+ * - 3 standard configurable plls: pll1, pll2 & pll3
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+ * - 2 exclusive plls: usb phy pll and sata phy pll
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+ * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
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+ * display and sdphy.
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+ * Each clock domain can select its own clock source from five clock sources,
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+ * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
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+ * clock of the group clock.
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+ * - dsp domain: gps, mf
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+ * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
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+ * - sys domain: security
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+ */
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+
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+struct clk_pll {
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+ struct clk_hw hw;
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+ unsigned short regofs; /* register offset */
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+};
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+
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+#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
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+
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+struct clk_dmn {
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+ struct clk_hw hw;
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+ signed char enable_bit; /* enable bit: 0 ~ 63 */
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+ unsigned short regofs; /* register offset */
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+};
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+
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+#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
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+
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+struct clk_std {
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+ struct clk_hw hw;
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+ signed char enable_bit; /* enable bit: 0 ~ 63 */
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+};
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+
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+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
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+
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+static int std_clk_is_enabled(struct clk_hw *hw);
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+static int std_clk_enable(struct clk_hw *hw);
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+static void std_clk_disable(struct clk_hw *hw);
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+
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+static inline unsigned long clkc_readl(unsigned reg)
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+{
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+ return readl(sirfsoc_clk_vbase + reg);
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+}
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+
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+static inline void clkc_writel(u32 val, unsigned reg)
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+{
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+ writel(val, sirfsoc_clk_vbase + reg);
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+}
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+
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+/*
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+ * std pll
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+ */
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+
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+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ unsigned long fin = parent_rate;
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+ struct clk_pll *clk = to_pllclk(hw);
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+ u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
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+ SIRFSOC_CLKC_PLL1_CFG0;
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+
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+ if (clkc_readl(regcfg2) & BIT(2)) {
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+ /* pll bypass mode */
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+ return fin;
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+ } else {
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+ /* fout = fin * nf / nr / od */
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+ u32 cfg0 = clkc_readl(clk->regofs);
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+ u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
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+ u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
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+ u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
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+ WARN_ON(fin % MHZ);
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+ return fin / MHZ * nf / nr / od * MHZ;
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+ }
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+}
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+
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+static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ unsigned long fin, nf, nr, od;
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+
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+ /*
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+ * fout = fin * nf / (nr * od);
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+ * set od = 1, nr = fin/MHz, so fout = nf * MHz
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+ */
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+ rate = rate - rate % MHZ;
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+
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+ nf = rate / MHZ;
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+ if (nf > BIT(13))
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+ nf = BIT(13);
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+ if (nf < 1)
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+ nf = 1;
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+
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+ fin = *parent_rate;
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+
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+ nr = fin / MHZ;
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+ if (nr > BIT(6))
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+ nr = BIT(6);
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+ od = 1;
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+
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+ return fin * nf / (nr * od);
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+}
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+
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+static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct clk_pll *clk = to_pllclk(hw);
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+ unsigned long fin, nf, nr, od, reg;
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+
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+ /*
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+ * fout = fin * nf / (nr * od);
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+ * set od = 1, nr = fin/MHz, so fout = nf * MHz
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+ */
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+
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+ nf = rate / MHZ;
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+ if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
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+ return -EINVAL;
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+
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+ fin = parent_rate;
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+ BUG_ON(fin < MHZ);
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+
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+ nr = fin / MHZ;
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+ BUG_ON((fin % MHZ) || nr > BIT(6));
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+
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+ od = 1;
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+
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+ reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
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+ clkc_writel(reg, clk->regofs);
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+
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+ reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
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+ clkc_writel((nf >> 1) - 1, reg);
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+
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+ reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
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+ while (!(clkc_readl(reg) & BIT(6)))
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+ cpu_relax();
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+
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+ return 0;
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+}
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+
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+static struct clk_ops std_pll_ops = {
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+ .recalc_rate = pll_clk_recalc_rate,
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+ .round_rate = pll_clk_round_rate,
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+ .set_rate = pll_clk_set_rate,
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+};
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+
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+static const char *pll_clk_parents[] = {
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+ "osc",
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+};
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+
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+static struct clk_init_data clk_pll1_init = {
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+ .name = "pll1",
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+ .ops = &std_pll_ops,
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+ .parent_names = pll_clk_parents,
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+ .num_parents = ARRAY_SIZE(pll_clk_parents),
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+};
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+
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+static struct clk_init_data clk_pll2_init = {
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+ .name = "pll2",
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+ .ops = &std_pll_ops,
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+ .parent_names = pll_clk_parents,
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+ .num_parents = ARRAY_SIZE(pll_clk_parents),
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+};
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+
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+static struct clk_init_data clk_pll3_init = {
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+ .name = "pll3",
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+ .ops = &std_pll_ops,
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+ .parent_names = pll_clk_parents,
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+ .num_parents = ARRAY_SIZE(pll_clk_parents),
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+};
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+
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+static struct clk_pll clk_pll1 = {
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+ .regofs = SIRFSOC_CLKC_PLL1_CFG0,
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+ .hw = {
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+ .init = &clk_pll1_init,
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+ },
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+};
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+
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+static struct clk_pll clk_pll2 = {
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+ .regofs = SIRFSOC_CLKC_PLL2_CFG0,
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+ .hw = {
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+ .init = &clk_pll2_init,
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+ },
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+};
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+
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+static struct clk_pll clk_pll3 = {
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+ .regofs = SIRFSOC_CLKC_PLL3_CFG0,
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+ .hw = {
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+ .init = &clk_pll3_init,
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+ },
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+};
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+
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+/*
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+ * usb uses specified pll
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+ */
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+
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+static int usb_pll_clk_enable(struct clk_hw *hw)
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+{
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+ u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
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+ reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
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+ writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
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+ while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
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+ SIRFSOC_USBPHY_PLL_LOCK))
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+ cpu_relax();
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+
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+ return 0;
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+}
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+
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+static void usb_pll_clk_disable(struct clk_hw *clk)
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+{
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+ u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
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+ reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
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+ writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
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+}
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+
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+static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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+{
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+ u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
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+ return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
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+}
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+
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+static struct clk_ops usb_pll_ops = {
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+ .enable = usb_pll_clk_enable,
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+ .disable = usb_pll_clk_disable,
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+ .recalc_rate = usb_pll_clk_recalc_rate,
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+};
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+
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+static struct clk_init_data clk_usb_pll_init = {
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+ .name = "usb_pll",
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+ .ops = &usb_pll_ops,
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+ .parent_names = pll_clk_parents,
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+ .num_parents = ARRAY_SIZE(pll_clk_parents),
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+};
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+
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+static struct clk_hw usb_pll_clk_hw = {
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+ .init = &clk_usb_pll_init,
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+};
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+
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+/*
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+ * clock domains - cpu, mem, sys/io, dsp, gfx
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+ */
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+
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+static const char *dmn_clk_parents[] = {
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+ "rtc",
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+ "osc",
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+ "pll1",
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+ "pll2",
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+ "pll3",
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+};
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+
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+static u8 dmn_clk_get_parent(struct clk_hw *hw)
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+{
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+ struct clk_dmn *clk = to_dmnclk(hw);
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+ u32 cfg = clkc_readl(clk->regofs);
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+
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+ /* parent of io domain can only be pll3 */
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+ if (strcmp(hw->init->name, "io") == 0)
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+ return 4;
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+
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+ WARN_ON((cfg & (BIT(3) - 1)) > 4);
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+
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+ return cfg & (BIT(3) - 1);
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+}
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+
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+static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
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+{
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+ struct clk_dmn *clk = to_dmnclk(hw);
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+ u32 cfg = clkc_readl(clk->regofs);
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+
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+ /* parent of io domain can only be pll3 */
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+ if (strcmp(hw->init->name, "io") == 0)
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+ return -EINVAL;
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+
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+ cfg &= ~(BIT(3) - 1);
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+ clkc_writel(cfg | parent, clk->regofs);
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+ /* BIT(3) - switching status: 1 - busy, 0 - done */
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+ while (clkc_readl(clk->regofs) & BIT(3))
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+ cpu_relax();
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+
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+ return 0;
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+}
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+
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+static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+
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+{
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+ unsigned long fin = parent_rate;
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+ struct clk_dmn *clk = to_dmnclk(hw);
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+
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+ u32 cfg = clkc_readl(clk->regofs);
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+
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+ if (cfg & BIT(24)) {
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+ /* fcd bypass mode */
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+ return fin;
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+ } else {
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+ /*
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+ * wait count: bit[19:16], hold count: bit[23:20]
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+ */
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+ u32 wait = (cfg >> 16) & (BIT(4) - 1);
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+ u32 hold = (cfg >> 20) & (BIT(4) - 1);
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+
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+ return fin / (wait + hold + 2);
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+ }
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+}
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+
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+static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ unsigned long fin;
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+ unsigned ratio, wait, hold;
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+ unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
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+
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+ fin = *parent_rate;
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+ ratio = fin / rate;
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+
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+ if (ratio < 2)
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+ ratio = 2;
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+ if (ratio > BIT(bits + 1))
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+ ratio = BIT(bits + 1);
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+
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+ wait = (ratio >> 1) - 1;
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+ hold = ratio - wait - 2;
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+
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+ return fin / (wait + hold + 2);
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+}
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+
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+static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct clk_dmn *clk = to_dmnclk(hw);
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+ unsigned long fin;
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+ unsigned ratio, wait, hold, reg;
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+ unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
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+
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+ fin = parent_rate;
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+ ratio = fin / rate;
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+
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+ if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
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+ return -EINVAL;
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+
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+ WARN_ON(fin % rate);
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+
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+ wait = (ratio >> 1) - 1;
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+ hold = ratio - wait - 2;
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+
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+ reg = clkc_readl(clk->regofs);
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|
+ reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
|
|
|
+ reg |= (wait << 16) | (hold << 20) | BIT(25);
|
|
|
+ clkc_writel(reg, clk->regofs);
|
|
|
+
|
|
|
+ /* waiting FCD been effective */
|
|
|
+ while (clkc_readl(clk->regofs) & BIT(25))
|
|
|
+ cpu_relax();
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct clk_ops msi_ops = {
|
|
|
+ .set_rate = dmn_clk_set_rate,
|
|
|
+ .round_rate = dmn_clk_round_rate,
|
|
|
+ .recalc_rate = dmn_clk_recalc_rate,
|
|
|
+ .set_parent = dmn_clk_set_parent,
|
|
|
+ .get_parent = dmn_clk_get_parent,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_mem_init = {
|
|
|
+ .name = "mem",
|
|
|
+ .ops = &msi_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_mem = {
|
|
|
+ .regofs = SIRFSOC_CLKC_MEM_CFG,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_mem_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_sys_init = {
|
|
|
+ .name = "sys",
|
|
|
+ .ops = &msi_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+ .flags = CLK_SET_RATE_GATE,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_sys = {
|
|
|
+ .regofs = SIRFSOC_CLKC_SYS_CFG,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_sys_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_io_init = {
|
|
|
+ .name = "io",
|
|
|
+ .ops = &msi_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_io = {
|
|
|
+ .regofs = SIRFSOC_CLKC_IO_CFG,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_io_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_ops cpu_ops = {
|
|
|
+ .set_parent = dmn_clk_set_parent,
|
|
|
+ .get_parent = dmn_clk_get_parent,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_cpu_init = {
|
|
|
+ .name = "cpu",
|
|
|
+ .ops = &cpu_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+ .flags = CLK_SET_RATE_PARENT,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_cpu = {
|
|
|
+ .regofs = SIRFSOC_CLKC_CPU_CFG,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_cpu_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_ops dmn_ops = {
|
|
|
+ .is_enabled = std_clk_is_enabled,
|
|
|
+ .enable = std_clk_enable,
|
|
|
+ .disable = std_clk_disable,
|
|
|
+ .set_rate = dmn_clk_set_rate,
|
|
|
+ .round_rate = dmn_clk_round_rate,
|
|
|
+ .recalc_rate = dmn_clk_recalc_rate,
|
|
|
+ .set_parent = dmn_clk_set_parent,
|
|
|
+ .get_parent = dmn_clk_get_parent,
|
|
|
+};
|
|
|
+
|
|
|
+/* dsp, gfx, mm, lcd and vpp domain */
|
|
|
+
|
|
|
+static struct clk_init_data clk_dsp_init = {
|
|
|
+ .name = "dsp",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_dsp = {
|
|
|
+ .regofs = SIRFSOC_CLKC_DSP_CFG,
|
|
|
+ .enable_bit = 0,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_dsp_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_gfx_init = {
|
|
|
+ .name = "gfx",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_gfx = {
|
|
|
+ .regofs = SIRFSOC_CLKC_GFX_CFG,
|
|
|
+ .enable_bit = 8,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_gfx_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_mm_init = {
|
|
|
+ .name = "mm",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_mm = {
|
|
|
+ .regofs = SIRFSOC_CLKC_MM_CFG,
|
|
|
+ .enable_bit = 9,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_mm_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_lcd_init = {
|
|
|
+ .name = "lcd",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_lcd = {
|
|
|
+ .regofs = SIRFSOC_CLKC_LCD_CFG,
|
|
|
+ .enable_bit = 10,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_lcd_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_vpp_init = {
|
|
|
+ .name = "vpp",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_vpp = {
|
|
|
+ .regofs = SIRFSOC_CLKC_LCD_CFG,
|
|
|
+ .enable_bit = 11,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_vpp_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_mmc01_init = {
|
|
|
+ .name = "mmc01",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_mmc01 = {
|
|
|
+ .regofs = SIRFSOC_CLKC_MMC_CFG,
|
|
|
+ .enable_bit = 59,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_mmc01_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_mmc23_init = {
|
|
|
+ .name = "mmc23",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_mmc23 = {
|
|
|
+ .regofs = SIRFSOC_CLKC_MMC_CFG,
|
|
|
+ .enable_bit = 60,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_mmc23_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_mmc45_init = {
|
|
|
+ .name = "mmc45",
|
|
|
+ .ops = &dmn_ops,
|
|
|
+ .parent_names = dmn_clk_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_dmn clk_mmc45 = {
|
|
|
+ .regofs = SIRFSOC_CLKC_MMC_CFG,
|
|
|
+ .enable_bit = 61,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_mmc45_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * peripheral controllers in io domain
|
|
|
+ */
|
|
|
+
|
|
|
+static int std_clk_is_enabled(struct clk_hw *hw)
|
|
|
+{
|
|
|
+ u32 reg;
|
|
|
+ int bit;
|
|
|
+ struct clk_std *clk = to_stdclk(hw);
|
|
|
+
|
|
|
+ bit = clk->enable_bit % 32;
|
|
|
+ reg = clk->enable_bit / 32;
|
|
|
+ reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
|
|
|
+
|
|
|
+ return !!(clkc_readl(reg) & BIT(bit));
|
|
|
+}
|
|
|
+
|
|
|
+static int std_clk_enable(struct clk_hw *hw)
|
|
|
+{
|
|
|
+ u32 val, reg;
|
|
|
+ int bit;
|
|
|
+ struct clk_std *clk = to_stdclk(hw);
|
|
|
+
|
|
|
+ BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
|
|
|
+
|
|
|
+ bit = clk->enable_bit % 32;
|
|
|
+ reg = clk->enable_bit / 32;
|
|
|
+ reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
|
|
|
+
|
|
|
+ val = clkc_readl(reg) | BIT(bit);
|
|
|
+ clkc_writel(val, reg);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void std_clk_disable(struct clk_hw *hw)
|
|
|
+{
|
|
|
+ u32 val, reg;
|
|
|
+ int bit;
|
|
|
+ struct clk_std *clk = to_stdclk(hw);
|
|
|
+
|
|
|
+ BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
|
|
|
+
|
|
|
+ bit = clk->enable_bit % 32;
|
|
|
+ reg = clk->enable_bit / 32;
|
|
|
+ reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
|
|
|
+
|
|
|
+ val = clkc_readl(reg) & ~BIT(bit);
|
|
|
+ clkc_writel(val, reg);
|
|
|
+}
|
|
|
+
|
|
|
+static const char *std_clk_io_parents[] = {
|
|
|
+ "io",
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_ops ios_ops = {
|
|
|
+ .is_enabled = std_clk_is_enabled,
|
|
|
+ .enable = std_clk_enable,
|
|
|
+ .disable = std_clk_disable,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_dmac0_init = {
|
|
|
+ .name = "dmac0",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_dmac0 = {
|
|
|
+ .enable_bit = 32,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_dmac0_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_dmac1_init = {
|
|
|
+ .name = "dmac1",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_dmac1 = {
|
|
|
+ .enable_bit = 33,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_dmac1_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_nand_init = {
|
|
|
+ .name = "nand",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_nand = {
|
|
|
+ .enable_bit = 34,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_nand_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_audio_init = {
|
|
|
+ .name = "audio",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_audio = {
|
|
|
+ .enable_bit = 35,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_audio_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_uart0_init = {
|
|
|
+ .name = "uart0",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_uart0 = {
|
|
|
+ .enable_bit = 36,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_uart0_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_uart1_init = {
|
|
|
+ .name = "uart1",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_uart1 = {
|
|
|
+ .enable_bit = 37,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_uart1_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_uart2_init = {
|
|
|
+ .name = "uart2",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_uart2 = {
|
|
|
+ .enable_bit = 38,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_uart2_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_usp0_init = {
|
|
|
+ .name = "usp0",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_usp0 = {
|
|
|
+ .enable_bit = 39,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_usp0_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_usp1_init = {
|
|
|
+ .name = "usp1",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_usp1 = {
|
|
|
+ .enable_bit = 40,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_usp1_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_usp2_init = {
|
|
|
+ .name = "usp2",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_usp2 = {
|
|
|
+ .enable_bit = 41,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_usp2_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_vip_init = {
|
|
|
+ .name = "vip",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_vip = {
|
|
|
+ .enable_bit = 42,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_vip_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_spi0_init = {
|
|
|
+ .name = "spi0",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_spi0 = {
|
|
|
+ .enable_bit = 43,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_spi0_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_spi1_init = {
|
|
|
+ .name = "spi1",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_spi1 = {
|
|
|
+ .enable_bit = 44,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_spi1_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_tsc_init = {
|
|
|
+ .name = "tsc",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_tsc = {
|
|
|
+ .enable_bit = 45,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_tsc_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_i2c0_init = {
|
|
|
+ .name = "i2c0",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_i2c0 = {
|
|
|
+ .enable_bit = 46,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_i2c0_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_i2c1_init = {
|
|
|
+ .name = "i2c1",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_i2c1 = {
|
|
|
+ .enable_bit = 47,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_i2c1_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_pwmc_init = {
|
|
|
+ .name = "pwmc",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_pwmc = {
|
|
|
+ .enable_bit = 48,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_pwmc_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_efuse_init = {
|
|
|
+ .name = "efuse",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_efuse = {
|
|
|
+ .enable_bit = 49,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_efuse_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_pulse_init = {
|
|
|
+ .name = "pulse",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_pulse = {
|
|
|
+ .enable_bit = 50,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_pulse_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static const char *std_clk_dsp_parents[] = {
|
|
|
+ "dsp",
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_gps_init = {
|
|
|
+ .name = "gps",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_dsp_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_gps = {
|
|
|
+ .enable_bit = 1,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_gps_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_mf_init = {
|
|
|
+ .name = "mf",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_io_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_mf = {
|
|
|
+ .enable_bit = 2,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_mf_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static const char *std_clk_sys_parents[] = {
|
|
|
+ "sys",
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_security_init = {
|
|
|
+ .name = "mf",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_sys_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_sys_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_security = {
|
|
|
+ .enable_bit = 19,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_security_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static const char *std_clk_usb_parents[] = {
|
|
|
+ "usb_pll",
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_usb0_init = {
|
|
|
+ .name = "usb0",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_usb_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_usb_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_usb0 = {
|
|
|
+ .enable_bit = 16,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_usb0_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_init_data clk_usb1_init = {
|
|
|
+ .name = "usb1",
|
|
|
+ .ops = &ios_ops,
|
|
|
+ .parent_names = std_clk_usb_parents,
|
|
|
+ .num_parents = ARRAY_SIZE(std_clk_usb_parents),
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_std clk_usb1 = {
|
|
|
+ .enable_bit = 17,
|
|
|
+ .hw = {
|
|
|
+ .init = &clk_usb1_init,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct of_device_id clkc_ids[] = {
|
|
|
+ { .compatible = "sirf,prima2-clkc" },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+static struct of_device_id rsc_ids[] = {
|
|
|
+ { .compatible = "sirf,prima2-rsc" },
|
|
|
+ {},
|
|
|
+};
|
|
|
+
|
|
|
+void __init sirfsoc_of_clk_init(void)
|
|
|
+{
|
|
|
+ struct clk *clk;
|
|
|
+ struct device_node *np;
|
|
|
+
|
|
|
+ np = of_find_matching_node(NULL, clkc_ids);
|
|
|
+ if (!np)
|
|
|
+ panic("unable to find compatible clkc node in dtb\n");
|
|
|
+
|
|
|
+ sirfsoc_clk_vbase = of_iomap(np, 0);
|
|
|
+ if (!sirfsoc_clk_vbase)
|
|
|
+ panic("unable to map clkc registers\n");
|
|
|
+
|
|
|
+ of_node_put(np);
|
|
|
+
|
|
|
+ np = of_find_matching_node(NULL, rsc_ids);
|
|
|
+ if (!np)
|
|
|
+ panic("unable to find compatible rsc node in dtb\n");
|
|
|
+
|
|
|
+ sirfsoc_rsc_vbase = of_iomap(np, 0);
|
|
|
+ if (!sirfsoc_rsc_vbase)
|
|
|
+ panic("unable to map rsc registers\n");
|
|
|
+
|
|
|
+ of_node_put(np);
|
|
|
+
|
|
|
+
|
|
|
+ /* These are always available (RTC and 26MHz OSC)*/
|
|
|
+ clk = clk_register_fixed_rate(NULL, "rtc", NULL,
|
|
|
+ CLK_IS_ROOT, 32768);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register_fixed_rate(NULL, "osc", NULL,
|
|
|
+ CLK_IS_ROOT, 26000000);
|
|
|
+ BUG_ON(!clk);
|
|
|
+
|
|
|
+ clk = clk_register(NULL, &clk_pll1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_pll2.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_pll3.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_mem.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_sys.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_security.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b8030000.security");
|
|
|
+ clk = clk_register(NULL, &clk_dsp.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_gps.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "a8010000.gps");
|
|
|
+ clk = clk_register(NULL, &clk_mf.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_io.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "io");
|
|
|
+ clk = clk_register(NULL, &clk_cpu.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "cpu");
|
|
|
+ clk = clk_register(NULL, &clk_uart0.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0050000.uart");
|
|
|
+ clk = clk_register(NULL, &clk_uart1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0060000.uart");
|
|
|
+ clk = clk_register(NULL, &clk_uart2.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0070000.uart");
|
|
|
+ clk = clk_register(NULL, &clk_tsc.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0110000.tsc");
|
|
|
+ clk = clk_register(NULL, &clk_i2c0.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00e0000.i2c");
|
|
|
+ clk = clk_register(NULL, &clk_i2c1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00f0000.i2c");
|
|
|
+ clk = clk_register(NULL, &clk_spi0.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00d0000.spi");
|
|
|
+ clk = clk_register(NULL, &clk_spi1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0170000.spi");
|
|
|
+ clk = clk_register(NULL, &clk_pwmc.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0130000.pwm");
|
|
|
+ clk = clk_register(NULL, &clk_efuse.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0140000.efusesys");
|
|
|
+ clk = clk_register(NULL, &clk_pulse.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0150000.pulsec");
|
|
|
+ clk = clk_register(NULL, &clk_dmac0.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
|
|
|
+ clk = clk_register(NULL, &clk_dmac1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
|
|
|
+ clk = clk_register(NULL, &clk_nand.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0030000.nand");
|
|
|
+ clk = clk_register(NULL, &clk_audio.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0040000.audio");
|
|
|
+ clk = clk_register(NULL, &clk_usp0.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0080000.usp");
|
|
|
+ clk = clk_register(NULL, &clk_usp1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b0090000.usp");
|
|
|
+ clk = clk_register(NULL, &clk_usp2.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00a0000.usp");
|
|
|
+ clk = clk_register(NULL, &clk_vip.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00c0000.vip");
|
|
|
+ clk = clk_register(NULL, &clk_gfx.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "98000000.graphics");
|
|
|
+ clk = clk_register(NULL, &clk_mm.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "a0000000.multimedia");
|
|
|
+ clk = clk_register(NULL, &clk_lcd.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "90010000.display");
|
|
|
+ clk = clk_register(NULL, &clk_vpp.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "90020000.vpp");
|
|
|
+ clk = clk_register(NULL, &clk_mmc01.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_mmc23.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_mmc45.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &usb_pll_clk_hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk = clk_register(NULL, &clk_usb0.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00e0000.usb");
|
|
|
+ clk = clk_register(NULL, &clk_usb1.hw);
|
|
|
+ BUG_ON(!clk);
|
|
|
+ clk_register_clkdev(clk, NULL, "b00f0000.usb");
|
|
|
+}
|
Olof Johansson