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@@ -78,6 +78,9 @@ struct atmel_mci_caps {
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bool has_highspeed;
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bool has_rwproof;
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bool has_odd_clk_div;
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+ bool has_bad_data_ordering;
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+ bool need_reset_after_xfer;
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+ bool need_blksz_mul_4;
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};
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struct atmel_mci_dma {
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@@ -121,6 +124,7 @@ struct atmel_mci_dma {
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* @queue: List of slots waiting for access to the controller.
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* @need_clock_update: Update the clock rate before the next request.
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* @need_reset: Reset controller before next request.
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+ * @timer: Timer to balance the data timeout error flag which cannot rise.
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* @mode_reg: Value of the MR register.
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* @cfg_reg: Value of the CFG register.
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* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
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@@ -197,6 +201,7 @@ struct atmel_mci {
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bool need_clock_update;
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bool need_reset;
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+ struct timer_list timer;
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u32 mode_reg;
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u32 cfg_reg;
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unsigned long bus_hz;
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@@ -493,6 +498,27 @@ static inline unsigned int atmci_get_version(struct atmel_mci *host)
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return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
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}
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+static void atmci_timeout_timer(unsigned long data)
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+{
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+ struct atmel_mci *host;
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+
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+ host = (struct atmel_mci *)data;
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+
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+ dev_dbg(&host->pdev->dev, "software timeout\n");
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+
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+ if (host->mrq->cmd->data) {
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+ host->mrq->cmd->data->error = -ETIMEDOUT;
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+ host->data = NULL;
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+ } else {
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+ host->mrq->cmd->error = -ETIMEDOUT;
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+ host->cmd = NULL;
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+ }
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+ host->need_reset = 1;
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+ host->state = STATE_END_REQUEST;
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+ smp_wmb();
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+ tasklet_schedule(&host->tasklet);
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+}
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+
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static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
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unsigned int ns)
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{
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@@ -692,13 +718,18 @@ static void atmci_pdc_cleanup(struct atmel_mci *host)
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static void atmci_pdc_complete(struct atmel_mci *host)
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{
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int transfer_size = host->data->blocks * host->data->blksz;
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+ int i;
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atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
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if ((!host->caps.has_rwproof)
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- && (host->data->flags & MMC_DATA_READ))
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+ && (host->data->flags & MMC_DATA_READ)) {
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+ if (host->caps.has_bad_data_ordering)
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+ for (i = 0; i < transfer_size; i++)
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+ host->buffer[i] = swab32(host->buffer[i]);
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sg_copy_from_buffer(host->data->sg, host->data->sg_len,
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host->buffer, transfer_size);
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+ }
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atmci_pdc_cleanup(host);
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@@ -819,6 +850,7 @@ atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
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u32 iflags, tmp;
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unsigned int sg_len;
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enum dma_data_direction dir;
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+ int i;
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data->error = -EINPROGRESS;
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@@ -848,9 +880,13 @@ atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
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sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
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if ((!host->caps.has_rwproof)
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- && (host->data->flags & MMC_DATA_WRITE))
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+ && (host->data->flags & MMC_DATA_WRITE)) {
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sg_copy_to_buffer(host->data->sg, host->data->sg_len,
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host->buffer, host->data_size);
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+ if (host->caps.has_bad_data_ordering)
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+ for (i = 0; i < host->data_size; i++)
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+ host->buffer[i] = swab32(host->buffer[i]);
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+ }
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if (host->data_size)
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atmci_pdc_set_both_buf(host,
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@@ -1013,7 +1049,7 @@ static void atmci_start_request(struct atmel_mci *host,
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host->cmd_status = 0;
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host->data_status = 0;
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- if (host->need_reset) {
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+ if (host->need_reset || host->caps.need_reset_after_xfer) {
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iflags = atmci_readl(host, ATMCI_IMR);
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iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
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atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
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@@ -1077,6 +1113,8 @@ static void atmci_start_request(struct atmel_mci *host,
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* prepared yet.)
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*/
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atmci_writel(host, ATMCI_IER, iflags);
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+
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+ mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
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}
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static void atmci_queue_request(struct atmel_mci *host,
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@@ -1342,6 +1380,8 @@ static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
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host->state = STATE_IDLE;
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}
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+ del_timer(&host->timer);
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+
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spin_unlock(&host->lock);
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mmc_request_done(prev_mmc, mrq);
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spin_lock(&host->lock);
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@@ -1364,7 +1404,12 @@ static void atmci_command_complete(struct atmel_mci *host,
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cmd->error = -EILSEQ;
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else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
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cmd->error = -EIO;
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- else
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+ else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
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+ if (host->caps.need_blksz_mul_4) {
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+ cmd->error = -EINVAL;
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+ host->need_reset = 1;
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+ }
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+ } else
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cmd->error = 0;
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}
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@@ -2121,6 +2166,9 @@ static void __init atmci_get_cap(struct atmel_mci *host)
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host->caps.has_highspeed = 0;
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host->caps.has_rwproof = 0;
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host->caps.has_odd_clk_div = 0;
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+ host->caps.has_bad_data_ordering = 1;
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+ host->caps.need_reset_after_xfer = 1;
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+ host->caps.need_blksz_mul_4 = 1;
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/* keep only major version number */
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switch (version & 0xf00) {
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@@ -2140,7 +2188,11 @@ static void __init atmci_get_cap(struct atmel_mci *host)
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host->caps.has_highspeed = 1;
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case 0x200:
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host->caps.has_rwproof = 1;
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+ host->caps.need_blksz_mul_4 = 0;
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case 0x100:
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+ host->caps.has_bad_data_ordering = 0;
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+ host->caps.need_reset_after_xfer = 0;
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+ case 0x0:
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break;
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default:
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host->caps.has_pdc = 0;
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@@ -2259,6 +2311,8 @@ static int __init atmci_probe(struct platform_device *pdev)
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}
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}
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+ setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
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+
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dev_info(&pdev->dev,
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"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
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host->mapbase, irq, nr_slots);
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