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@@ -88,9 +88,6 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
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pci_write_config_byte(dev, drwtim_regs[drive->dn],
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(t.active << 4) | t.recover);
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- if (mode >= XFER_SW_DMA_0)
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- return;
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-
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/*
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* The primary channel has individual address setup timing registers
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* for each drive and the hardware selects the slowest timing itself.
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@@ -100,11 +97,17 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
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if (hwif->channel) {
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ide_drive_t *pair = ide_get_pair_dev(drive);
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- ide_set_drivedata(drive, (void *)(unsigned long)t.setup);
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+ if (pair) {
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+ struct ide_timing tp;
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- if (pair)
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- t.setup = max_t(u8, t.setup,
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- (unsigned long)ide_get_drivedata(pair));
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+ ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
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+ ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
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+ if (pair->dma_mode) {
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+ ide_timing_compute(pair, pair->dma_mode,
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+ &tp, T, 0);
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+ ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
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+ }
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+ }
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}
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if (t.setup > 5) /* shouldn't actually happen... */
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