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@@ -1,11 +1,7 @@
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-config CAVIUM_OCTEON_SPECIFIC_OPTIONS
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- bool "Enable Octeon specific options"
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- depends on CPU_CAVIUM_OCTEON
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- default "y"
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+if CPU_CAVIUM_OCTEON
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config CAVIUM_CN63XXP1
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bool "Enable CN63XXP1 errata worarounds"
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- depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "n"
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help
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The CN63XXP1 chip requires build time workarounds to
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@@ -16,7 +12,6 @@ config CAVIUM_CN63XXP1
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config CAVIUM_OCTEON_2ND_KERNEL
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bool "Build the kernel to be used as a 2nd kernel on the same chip"
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- depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "n"
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help
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This option configures this kernel to be linked at a different
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@@ -26,7 +21,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
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config CAVIUM_OCTEON_HW_FIX_UNALIGNED
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bool "Enable hardware fixups of unaligned loads and stores"
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- depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "y"
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help
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Configure the Octeon hardware to automatically fix unaligned loads
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@@ -38,7 +32,6 @@ config CAVIUM_OCTEON_HW_FIX_UNALIGNED
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config CAVIUM_OCTEON_CVMSEG_SIZE
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int "Number of L1 cache lines reserved for CVMSEG memory"
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- depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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range 0 54
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default 1
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help
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@@ -50,7 +43,6 @@ config CAVIUM_OCTEON_CVMSEG_SIZE
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config CAVIUM_OCTEON_LOCK_L2
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bool "Lock often used kernel code in the L2"
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- depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "y"
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help
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Enable locking parts of the kernel into the L2 cache.
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@@ -93,7 +85,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY
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config ARCH_SPARSEMEM_ENABLE
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def_bool y
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select SPARSEMEM_STATIC
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- depends on CPU_CAVIUM_OCTEON
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config CAVIUM_OCTEON_HELPER
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def_bool y
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@@ -107,6 +98,8 @@ config NEED_SG_DMA_LENGTH
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config SWIOTLB
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def_bool y
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- depends on CPU_CAVIUM_OCTEON
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select IOMMU_HELPER
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select NEED_SG_DMA_LENGTH
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+
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+
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+endif # CPU_CAVIUM_OCTEON
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