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@@ -323,6 +323,9 @@ struct intel_limit {
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#define IRONLAKE_DP_P1_MIN 1
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#define IRONLAKE_DP_P1_MAX 2
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+/* FDI */
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+#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
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+
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static bool
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intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *best_clock);
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@@ -2421,8 +2424,8 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
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struct drm_device *dev = crtc->dev;
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if (HAS_PCH_SPLIT(dev)) {
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/* FDI link clock is fixed at 2.7G */
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- if (mode->clock * 3 > 27000 * 4)
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- return MODE_CLOCK_HIGH;
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+ if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
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+ return false;
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}
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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