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@@ -641,9 +641,11 @@ static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
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void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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- u32 a;
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+ int nq = trans->cfg->base_params->num_of_queues;
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int chan;
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u32 reg_val;
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+ int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
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+ SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
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/* make sure all queue are not stopped/used */
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memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
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@@ -655,20 +657,10 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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WARN_ON(scd_base_addr != 0 &&
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scd_base_addr != trans_pcie->scd_base_addr);
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- a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
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- /* reset conext data memory */
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- for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
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- a += 4)
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- iwl_trans_write_mem32(trans, a, 0);
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- /* reset tx status memory */
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- for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
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- a += 4)
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- iwl_trans_write_mem32(trans, a, 0);
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- for (; a < trans_pcie->scd_base_addr +
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- SCD_TRANS_TBL_OFFSET_QUEUE(
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- trans->cfg->base_params->num_of_queues);
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- a += 4)
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- iwl_trans_write_mem32(trans, a, 0);
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+ /* reset context data, TX status and translation data */
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+ iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
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+ SCD_CONTEXT_MEM_LOWER_BOUND,
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+ NULL, clear_dwords);
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iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
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trans_pcie->scd_bc_tbls.dma >> 10);
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