ARM: dt: tegra seaboard: fix I2C2 SCL rate · 22bd1f7ef4 - Gogs

ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Stephen Warren 13 years ago

parent

b46b0b54de

commit

22bd1f7ef4

1 changed files with 1 additions and 1 deletions

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arch/arm/boot/dts/tegra-seaboard.dts
							 
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				@@ -281,7 +281,7 @@
			
				 	};
			
				 	i2c@7000c400 {
			
				-		clock-frequency = <400000>;
			
				+		clock-frequency = <100000>;
			
				 	};
			
				 	i2c@7000c500 {