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@@ -20,6 +20,9 @@
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#include <linux/delay.h>
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#include <linux/percpu.h>
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#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_address.h>
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+#include <linux/clocksource.h>
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#include <asm/arch_timer.h>
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#include <asm/localtimer.h>
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@@ -28,9 +31,36 @@
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#include <mach/map.h>
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#include <mach/irqs.h>
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-#include <mach/regs-mct.h>
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#include <asm/mach/time.h>
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+#define EXYNOS4_MCTREG(x) (x)
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+#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
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+#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
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+#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
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+#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
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+#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
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+#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
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+#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
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+#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
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+#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
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+#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
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+#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
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+#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
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+#define EXYNOS4_MCT_L_MASK (0xffffff00)
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+
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+#define MCT_L_TCNTB_OFFSET (0x00)
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+#define MCT_L_ICNTB_OFFSET (0x08)
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+#define MCT_L_TCON_OFFSET (0x20)
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+#define MCT_L_INT_CSTAT_OFFSET (0x30)
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+#define MCT_L_INT_ENB_OFFSET (0x34)
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+#define MCT_L_WSTAT_OFFSET (0x40)
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+#define MCT_G_TCON_START (1 << 8)
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+#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
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+#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
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+#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
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+#define MCT_L_TCON_INT_START (1 << 1)
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+#define MCT_L_TCON_TIMER_START (1 << 0)
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+
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#define TICK_BASE_CNT 1
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enum {
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@@ -38,64 +68,75 @@ enum {
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MCT_INT_PPI
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};
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+enum {
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+ MCT_G0_IRQ,
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+ MCT_G1_IRQ,
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+ MCT_G2_IRQ,
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+ MCT_G3_IRQ,
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+ MCT_L0_IRQ,
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+ MCT_L1_IRQ,
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+ MCT_L2_IRQ,
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+ MCT_L3_IRQ,
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+ MCT_NR_IRQS,
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+};
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+
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+static void __iomem *reg_base;
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static unsigned long clk_rate;
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static unsigned int mct_int_type;
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+static int mct_irqs[MCT_NR_IRQS];
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struct mct_clock_event_device {
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struct clock_event_device *evt;
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- void __iomem *base;
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+ unsigned long base;
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char name[10];
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};
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-static void exynos4_mct_write(unsigned int value, void *addr)
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+static void exynos4_mct_write(unsigned int value, unsigned long offset)
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{
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- void __iomem *stat_addr;
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+ unsigned long stat_addr;
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u32 mask;
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u32 i;
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- __raw_writel(value, addr);
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+ __raw_writel(value, reg_base + offset);
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- if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
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- u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
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- switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
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- case (u32) MCT_L_TCON_OFFSET:
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- stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
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+ if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
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+ stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
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+ switch (offset & EXYNOS4_MCT_L_MASK) {
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+ case MCT_L_TCON_OFFSET:
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mask = 1 << 3; /* L_TCON write status */
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break;
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- case (u32) MCT_L_ICNTB_OFFSET:
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- stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
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+ case MCT_L_ICNTB_OFFSET:
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mask = 1 << 1; /* L_ICNTB write status */
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break;
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- case (u32) MCT_L_TCNTB_OFFSET:
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- stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
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+ case MCT_L_TCNTB_OFFSET:
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mask = 1 << 0; /* L_TCNTB write status */
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break;
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default:
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return;
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}
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} else {
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- switch ((u32) addr) {
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- case (u32) EXYNOS4_MCT_G_TCON:
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+ switch (offset) {
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+ case EXYNOS4_MCT_G_TCON:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 16; /* G_TCON write status */
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break;
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- case (u32) EXYNOS4_MCT_G_COMP0_L:
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+ case EXYNOS4_MCT_G_COMP0_L:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 0; /* G_COMP0_L write status */
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break;
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- case (u32) EXYNOS4_MCT_G_COMP0_U:
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+ case EXYNOS4_MCT_G_COMP0_U:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 1; /* G_COMP0_U write status */
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break;
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- case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
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+ case EXYNOS4_MCT_G_COMP0_ADD_INCR:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
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break;
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- case (u32) EXYNOS4_MCT_G_CNT_L:
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+ case EXYNOS4_MCT_G_CNT_L:
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stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
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mask = 1 << 0; /* G_CNT_L write status */
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break;
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- case (u32) EXYNOS4_MCT_G_CNT_U:
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+ case EXYNOS4_MCT_G_CNT_U:
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stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
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mask = 1 << 1; /* G_CNT_U write status */
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break;
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@@ -106,12 +147,12 @@ static void exynos4_mct_write(unsigned int value, void *addr)
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/* Wait maximum 1 ms until written values are applied */
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for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
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- if (__raw_readl(stat_addr) & mask) {
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- __raw_writel(mask, stat_addr);
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+ if (__raw_readl(reg_base + stat_addr) & mask) {
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+ __raw_writel(mask, reg_base + stat_addr);
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return;
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}
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- panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
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+ panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
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}
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/* Clocksource handling */
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@@ -122,7 +163,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
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exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
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exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
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- reg = __raw_readl(EXYNOS4_MCT_G_TCON);
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+ reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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reg |= MCT_G_TCON_START;
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
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}
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@@ -130,12 +171,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
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static cycle_t exynos4_frc_read(struct clocksource *cs)
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{
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unsigned int lo, hi;
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- u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
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+ u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
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do {
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hi = hi2;
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- lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
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- hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
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+ lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
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+ hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
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} while (hi != hi2);
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return ((cycle_t)hi << 32) | lo;
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@@ -167,7 +208,7 @@ static void exynos4_mct_comp0_stop(void)
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{
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unsigned int tcon;
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- tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
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+ tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
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exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
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@@ -180,7 +221,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
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unsigned int tcon;
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cycle_t comp_cycle;
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- tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
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+ tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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tcon |= MCT_G_TCON_COMP0_AUTO_INC;
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@@ -257,11 +298,7 @@ static void exynos4_clockevent_init(void)
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mct_comp_device.cpumask = cpumask_of(0);
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clockevents_config_and_register(&mct_comp_device, clk_rate,
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0xf, 0xffffffff);
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-
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- if (soc_is_exynos5250())
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- setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
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- else
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- setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
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+ setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
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}
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#ifdef CONFIG_LOCAL_TIMERS
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@@ -273,12 +310,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
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{
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unsigned long tmp;
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unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
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- void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
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+ unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
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- tmp = __raw_readl(addr);
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+ tmp = __raw_readl(reg_base + offset);
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if (tmp & mask) {
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tmp &= ~mask;
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- exynos4_mct_write(tmp, addr);
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+ exynos4_mct_write(tmp, offset);
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}
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}
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@@ -297,7 +334,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
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/* enable MCT tick interrupt */
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
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- tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
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+ tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
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tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
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MCT_L_TCON_INTERVAL_MODE;
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exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
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@@ -349,7 +386,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
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exynos4_mct_tick_stop(mevt);
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/* Clear the MCT tick interrupt */
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- if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
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+ if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
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return 1;
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} else {
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@@ -385,7 +422,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
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{
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struct mct_clock_event_device *mevt;
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unsigned int cpu = smp_processor_id();
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- int mct_lx_irq;
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mevt = this_cpu_ptr(&percpu_mct_tick);
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mevt->evt = evt;
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@@ -406,21 +442,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
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if (mct_int_type == MCT_INT_SPI) {
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if (cpu == 0) {
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- mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
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- EXYNOS5_IRQ_MCT_L0;
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mct_tick0_event_irq.dev_id = mevt;
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- evt->irq = mct_lx_irq;
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- setup_irq(mct_lx_irq, &mct_tick0_event_irq);
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+ evt->irq = mct_irqs[MCT_L0_IRQ];
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+ setup_irq(evt->irq, &mct_tick0_event_irq);
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} else {
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- mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
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- EXYNOS5_IRQ_MCT_L1;
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mct_tick1_event_irq.dev_id = mevt;
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- evt->irq = mct_lx_irq;
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- setup_irq(mct_lx_irq, &mct_tick1_event_irq);
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- irq_set_affinity(mct_lx_irq, cpumask_of(1));
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+ evt->irq = mct_irqs[MCT_L1_IRQ];
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+ setup_irq(evt->irq, &mct_tick1_event_irq);
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+ irq_set_affinity(evt->irq, cpumask_of(1));
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}
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} else {
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- enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
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+ enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
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}
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return 0;
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@@ -436,7 +468,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
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else
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remove_irq(evt->irq, &mct_tick1_event_irq);
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else
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- disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
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+ disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
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}
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static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
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@@ -445,41 +477,80 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
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};
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#endif /* CONFIG_LOCAL_TIMERS */
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-static void __init exynos4_timer_resources(void)
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+static void __init exynos4_timer_resources(void __iomem *base)
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{
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struct clk *mct_clk;
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mct_clk = clk_get(NULL, "xtal");
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clk_rate = clk_get_rate(mct_clk);
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+ reg_base = base;
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+ if (!reg_base)
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+ panic("%s: unable to ioremap mct address space\n", __func__);
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+
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#ifdef CONFIG_LOCAL_TIMERS
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if (mct_int_type == MCT_INT_PPI) {
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int err;
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- err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
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+ err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
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exynos4_mct_tick_isr, "MCT",
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&percpu_mct_tick);
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WARN(err, "MCT: can't request IRQ %d (%d)\n",
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- EXYNOS_IRQ_MCT_LOCALTIMER, err);
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+ mct_irqs[MCT_L0_IRQ], err);
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}
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local_timer_register(&exynos4_mct_tick_ops);
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#endif /* CONFIG_LOCAL_TIMERS */
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}
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-void __init exynos4_timer_init(void)
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+void __init mct_init(void)
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{
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- if (soc_is_exynos5440()) {
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- arch_timer_of_register();
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- return;
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+ if (soc_is_exynos4210()) {
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+ mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
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+ mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
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+ mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
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+ mct_int_type = MCT_INT_SPI;
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|
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+ } else {
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|
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+ panic("unable to determine mct controller type\n");
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|
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}
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|
|
|
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- if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
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- mct_int_type = MCT_INT_SPI;
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- else
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- mct_int_type = MCT_INT_PPI;
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|
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+ exynos4_timer_resources(S5P_VA_SYSTIMER);
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|
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+ exynos4_clocksource_init();
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|
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+ exynos4_clockevent_init();
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|
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+}
|
|
|
|
|
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- exynos4_timer_resources();
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|
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+static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
|
|
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+{
|
|
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+ u32 nr_irqs, i;
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|
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+
|
|
|
+ mct_int_type = int_type;
|
|
|
+
|
|
|
+ /* This driver uses only one global timer interrupt */
|
|
|
+ mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Find out the number of local irqs specified. The local
|
|
|
+ * timer irqs are specified after the four global timer
|
|
|
+ * irqs are specified.
|
|
|
+ */
|
|
|
+ nr_irqs = of_irq_count(np);
|
|
|
+ for (i = MCT_L0_IRQ; i < nr_irqs; i++)
|
|
|
+ mct_irqs[i] = irq_of_parse_and_map(np, i);
|
|
|
+
|
|
|
+ exynos4_timer_resources(of_iomap(np, 0));
|
|
|
exynos4_clocksource_init();
|
|
|
exynos4_clockevent_init();
|
|
|
}
|
|
|
+
|
|
|
+
|
|
|
+static void __init mct_init_spi(struct device_node *np)
|
|
|
+{
|
|
|
+ return mct_init_dt(np, MCT_INT_SPI);
|
|
|
+}
|
|
|
+
|
|
|
+static void __init mct_init_ppi(struct device_node *np)
|
|
|
+{
|
|
|
+ return mct_init_dt(np, MCT_INT_PPI);
|
|
|
+}
|
|
|
+CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
|
|
|
+CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
|
Arnd Bergmann