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@@ -199,6 +199,7 @@
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#define ACLKXE BIT(5)
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#define TX_ASYNC BIT(6)
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#define ACLKXPOL BIT(7)
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+#define ACLKXDIV_MASK 0x1f
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/*
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* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
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@@ -207,6 +208,7 @@
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#define ACLKRE BIT(5)
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#define RX_ASYNC BIT(6)
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#define ACLKRPOL BIT(7)
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+#define ACLKRDIV_MASK 0x1f
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/*
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* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
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@@ -215,6 +217,7 @@
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#define AHCLKXDIV(val) (val)
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#define AHCLKXPOL BIT(14)
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#define AHCLKXE BIT(15)
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+#define AHCLKXDIV_MASK 0xfff
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/*
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* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
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@@ -223,6 +226,7 @@
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#define AHCLKRDIV(val) (val)
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#define AHCLKRPOL BIT(14)
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#define AHCLKRE BIT(15)
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+#define AHCLKRDIV_MASK 0xfff
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/*
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* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
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@@ -473,6 +477,23 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
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void __iomem *base = dev->base;
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+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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+ case SND_SOC_DAIFMT_DSP_B:
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+ case SND_SOC_DAIFMT_AC97:
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+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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+ break;
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+ default:
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+ /* configure a full-word SYNC pulse (LRCLK) */
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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+
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+ /* make 1st data bit occur one ACLK cycle after the frame sync */
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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+ break;
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+ }
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+
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* codec is clock and frame slave */
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@@ -482,8 +503,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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- mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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- ACLKX | AHCLKX | AFSX);
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+ mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, ACLKX | AFSX);
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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/* codec is clock master and frame slave */
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@@ -554,6 +574,50 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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return 0;
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}
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+static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
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+{
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+ struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
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+
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+ switch (div_id) {
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+ case 0: /* MCLK divider */
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+ mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
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+ AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
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+ mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
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+ AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
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+ break;
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+
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+ case 1: /* BCLK divider */
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+ mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
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+ ACLKXDIV(div - 1), ACLKXDIV_MASK);
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+ mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
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+ ACLKRDIV(div - 1), ACLKRDIV_MASK);
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+ break;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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+ unsigned int freq, int dir)
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+{
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+ struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
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+
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+ if (dir == SND_SOC_CLOCK_OUT) {
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
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+ mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
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+ } else {
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+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
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+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
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+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
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+ }
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+
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+ return 0;
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+}
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+
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static int davinci_config_channel_size(struct davinci_audio_dev *dev,
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int channel_size)
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{
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@@ -709,8 +773,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/* bit stream is MSB first with no delay */
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/* DSP_B mode */
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- mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
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- AHCLKXE);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
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mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
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@@ -720,14 +782,10 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
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else
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printk(KERN_ERR "playback tdm slot %d not supported\n",
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dev->tdm_slots);
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-
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- mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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} else {
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/* bit stream is MSB first with no delay */
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/* DSP_B mode */
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mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
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- mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
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- AHCLKRE);
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mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
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if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
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@@ -736,8 +794,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
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else
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printk(KERN_ERR "capture tdm slot %d not supported\n",
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dev->tdm_slots);
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-
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- mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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}
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}
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@@ -809,6 +865,14 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
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word_length = DAVINCI_AUDIO_WORD_16;
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break;
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+ case SNDRV_PCM_FORMAT_U24_3LE:
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+ case SNDRV_PCM_FORMAT_S24_3LE:
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+ dma_params->data_type = 3;
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+ word_length = DAVINCI_AUDIO_WORD_24;
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+ break;
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+
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+ case SNDRV_PCM_FORMAT_U24_LE:
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+ case SNDRV_PCM_FORMAT_S24_LE:
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case SNDRV_PCM_FORMAT_U32_LE:
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case SNDRV_PCM_FORMAT_S32_LE:
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dma_params->data_type = 4;
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@@ -880,13 +944,18 @@ static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
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.trigger = davinci_mcasp_trigger,
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.hw_params = davinci_mcasp_hw_params,
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.set_fmt = davinci_mcasp_set_dai_fmt,
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-
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+ .set_clkdiv = davinci_mcasp_set_clkdiv,
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+ .set_sysclk = davinci_mcasp_set_sysclk,
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};
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#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_U8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_U16_LE | \
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+ SNDRV_PCM_FMTBIT_S24_LE | \
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+ SNDRV_PCM_FMTBIT_U24_LE | \
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+ SNDRV_PCM_FMTBIT_S24_3LE | \
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+ SNDRV_PCM_FMTBIT_U24_3LE | \
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SNDRV_PCM_FMTBIT_S32_LE | \
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SNDRV_PCM_FMTBIT_U32_LE)
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@@ -1098,6 +1167,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
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dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
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dma_data->asp_chan_q = pdata->asp_chan_q;
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dma_data->ram_chan_q = pdata->ram_chan_q;
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+ dma_data->sram_pool = pdata->sram_pool;
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dma_data->sram_size = pdata->sram_size_playback;
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dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
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mem->start);
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@@ -1115,6 +1185,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
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dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
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dma_data->asp_chan_q = pdata->asp_chan_q;
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dma_data->ram_chan_q = pdata->ram_chan_q;
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+ dma_data->sram_pool = pdata->sram_pool;
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dma_data->sram_size = pdata->sram_size_capture;
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dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
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mem->start);
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