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@@ -117,7 +117,11 @@ static struct _intel_private {
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* popup and for the GTT.
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*/
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int gtt_entries; /* i830+ */
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- void __iomem *flush_page;
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+ union {
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+ void __iomem *i9xx_flush_page;
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+ void *i8xx_flush_page;
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+ };
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+ struct page *i8xx_page;
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struct resource ifp_resource;
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} intel_private;
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@@ -579,6 +583,44 @@ static void intel_i830_init_gtt_entries(void)
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intel_private.gtt_entries = gtt_entries;
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}
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+static void intel_i830_fini_flush(void)
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+{
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+ kunmap(intel_private.i8xx_page);
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+ intel_private.i8xx_flush_page = NULL;
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+ unmap_page_from_agp(intel_private.i8xx_page);
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+ flush_agp_mappings();
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+
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+ __free_page(intel_private.i8xx_page);
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+}
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+
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+static void intel_i830_setup_flush(void)
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+{
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+
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+ intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
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+ if (!intel_private.i8xx_page) {
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+ return;
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+ }
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+
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+ /* make page uncached */
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+ map_page_into_agp(intel_private.i8xx_page);
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+ flush_agp_mappings();
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+
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+ intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
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+ if (!intel_private.i8xx_flush_page)
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+ intel_i830_fini_flush();
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+}
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+
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+static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
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+{
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+ unsigned int *pg = intel_private.i8xx_flush_page;
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+ int i;
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+
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+ for (i = 0; i < 256; i+=2)
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+ *(pg + i) = i;
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+
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+ wmb();
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+}
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+
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/* The intel i830 automatically initializes the agp aperture during POST.
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* Use the memory already set aside for in the GTT.
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*/
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@@ -679,6 +721,8 @@ static int intel_i830_configure(void)
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}
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global_cache_flush();
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+
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+ intel_i830_setup_flush();
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return 0;
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}
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@@ -778,11 +822,8 @@ static int intel_alloc_chipset_flush_resource(void)
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ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
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PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
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pcibios_align_resource, agp_bridge->dev);
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- if (ret != 0)
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- return ret;
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- printk("intel priv bus start %08lx\n", intel_private.ifp_resource.start);
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- return 0;
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+ return ret;
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}
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static void intel_i915_setup_chipset_flush(void)
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@@ -822,7 +863,6 @@ static void intel_i965_g33_setup_chipset_flush(void)
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pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32));
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pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
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- intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
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} else {
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u64 l64;
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@@ -833,12 +873,33 @@ static void intel_i965_g33_setup_chipset_flush(void)
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intel_private.ifp_resource.end = l64 + PAGE_SIZE;
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ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
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if (!ret) {
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- intel_private.ifp_resource.start = 0;
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- printk("Failed inserting resource into tree\n");
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+ printk("Failed inserting resource into tree - continuing\n");
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}
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}
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}
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+static void intel_i9xx_setup_flush(void)
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+{
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+ /* setup a resource for this object */
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+ memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
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+
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+ intel_private.ifp_resource.name = "Intel Flush Page";
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+ intel_private.ifp_resource.flags = IORESOURCE_MEM;
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+
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+ /* Setup chipset flush for 915 */
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+ if (IS_I965 || IS_G33) {
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+ intel_i965_g33_setup_chipset_flush();
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+ } else {
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+ intel_i915_setup_chipset_flush();
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+ }
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+
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+ if (intel_private.ifp_resource.start) {
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+ intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
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+ if (!intel_private.i9xx_flush_page)
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+ printk("unable to ioremap flush page - no chipset flushing");
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+ }
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+}
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+
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static int intel_i915_configure(void)
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{
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struct aper_size_info_fixed *current_size;
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@@ -868,40 +929,23 @@ static int intel_i915_configure(void)
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global_cache_flush();
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- /* setup a resource for this object */
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- memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource));
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-
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- intel_private.ifp_resource.name = "Intel Flush Page";
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- intel_private.ifp_resource.flags = IORESOURCE_MEM;
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-
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- /* Setup chipset flush for 915 */
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- if (IS_I965 || IS_G33) {
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- intel_i965_g33_setup_chipset_flush();
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- } else {
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- intel_i915_setup_chipset_flush();
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- }
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-
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- if (intel_private.ifp_resource.start) {
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- intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
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- if (!intel_private.flush_page)
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- printk("unable to ioremap flush page - no chipset flushing");
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- }
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+ intel_i9xx_setup_flush();
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return 0;
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}
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static void intel_i915_cleanup(void)
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{
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- if (intel_private.flush_page)
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- iounmap(intel_private.flush_page);
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+ if (intel_private.i9xx_flush_page)
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+ iounmap(intel_private.i9xx_flush_page);
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iounmap(intel_private.gtt);
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iounmap(intel_private.registers);
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}
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static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
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{
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- if (intel_private.flush_page)
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- writel(1, intel_private.flush_page);
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+ if (intel_private.i9xx_flush_page)
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+ writel(1, intel_private.i9xx_flush_page);
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}
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static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
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@@ -1395,6 +1439,8 @@ static int intel_845_configure(void)
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pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
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/* clear any possible error conditions */
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pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
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+
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+ intel_i830_setup_flush();
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return 0;
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}
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@@ -1651,6 +1697,7 @@ static const struct agp_bridge_driver intel_830_driver = {
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_type_to_mask_type = intel_i830_type_to_mask_type,
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+ .chipset_flush = intel_i830_chipset_flush,
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};
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static const struct agp_bridge_driver intel_820_driver = {
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@@ -1747,6 +1794,7 @@ static const struct agp_bridge_driver intel_845_driver = {
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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+ .chipset_flush = intel_i830_chipset_flush,
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};
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static const struct agp_bridge_driver intel_850_driver = {
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