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@@ -32,6 +32,7 @@
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#include <linux/slab.h>
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#include <net/mac80211.h>
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#include "iwl-eeprom.h"
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+#include "iwl-agn.h"
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-sta.h"
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@@ -85,6 +86,154 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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txq->need_update = 0;
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}
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+static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
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+{
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+ struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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+
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+ dma_addr_t addr = get_unaligned_le32(&tb->lo);
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+ if (sizeof(dma_addr_t) > sizeof(u32))
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+ addr |=
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+ ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
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+
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+ return addr;
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+}
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+
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+static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
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+{
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+ struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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+
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+ return le16_to_cpu(tb->hi_n_len) >> 4;
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+}
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+
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+static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
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+ dma_addr_t addr, u16 len)
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+{
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+ struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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+ u16 hi_n_len = len << 4;
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+
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+ put_unaligned_le32(addr, &tb->lo);
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+ if (sizeof(dma_addr_t) > sizeof(u32))
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+ hi_n_len |= ((addr >> 16) >> 16) & 0xF;
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+
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+ tb->hi_n_len = cpu_to_le16(hi_n_len);
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+
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+ tfd->num_tbs = idx + 1;
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+}
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+
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+static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
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+{
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+ return tfd->num_tbs & 0x1f;
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+}
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+
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+/**
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+ * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
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+ * @priv - driver private data
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+ * @txq - tx queue
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+ *
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+ * Does NOT advance any TFD circular buffer read/write indexes
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+ * Does NOT free the TFD itself (which is within circular buffer)
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+ */
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+void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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+{
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+ struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
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+ struct iwl_tfd *tfd;
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+ struct pci_dev *dev = priv->pci_dev;
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+ int index = txq->q.read_ptr;
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+ int i;
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+ int num_tbs;
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+
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+ tfd = &tfd_tmp[index];
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+
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+ /* Sanity check on number of chunks */
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+ num_tbs = iwl_tfd_get_num_tbs(tfd);
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+
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+ if (num_tbs >= IWL_NUM_OF_TBS) {
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+ IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
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+ /* @todo issue fatal error, it is quite serious situation */
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+ return;
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+ }
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+
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+ /* Unmap tx_cmd */
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+ if (num_tbs)
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+ pci_unmap_single(dev,
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+ dma_unmap_addr(&txq->meta[index], mapping),
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+ dma_unmap_len(&txq->meta[index], len),
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+ PCI_DMA_BIDIRECTIONAL);
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+
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+ /* Unmap chunks, if any. */
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+ for (i = 1; i < num_tbs; i++)
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+ pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
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+ iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
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+
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+ /* free SKB */
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+ if (txq->txb) {
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+ struct sk_buff *skb;
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+
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+ skb = txq->txb[txq->q.read_ptr].skb;
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+
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+ /* can be called from irqs-disabled context */
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+ if (skb) {
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+ dev_kfree_skb_any(skb);
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+ txq->txb[txq->q.read_ptr].skb = NULL;
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+ }
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+ }
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+}
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+
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+int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
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+ struct iwl_tx_queue *txq,
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+ dma_addr_t addr, u16 len,
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+ u8 reset, u8 pad)
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+{
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+ struct iwl_queue *q;
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+ struct iwl_tfd *tfd, *tfd_tmp;
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+ u32 num_tbs;
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+
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+ q = &txq->q;
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+ tfd_tmp = (struct iwl_tfd *)txq->tfds;
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+ tfd = &tfd_tmp[q->write_ptr];
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+
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+ if (reset)
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+ memset(tfd, 0, sizeof(*tfd));
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+
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+ num_tbs = iwl_tfd_get_num_tbs(tfd);
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+
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+ /* Each TFD can point to a maximum 20 Tx buffers */
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+ if (num_tbs >= IWL_NUM_OF_TBS) {
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+ IWL_ERR(priv, "Error can not send more than %d chunks\n",
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+ IWL_NUM_OF_TBS);
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+ return -EINVAL;
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+ }
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+
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+ if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
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+ return -EINVAL;
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+
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+ if (unlikely(addr & ~IWL_TX_DMA_MASK))
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+ IWL_ERR(priv, "Unaligned address = %llx\n",
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+ (unsigned long long)addr);
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+
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+ iwl_tfd_set_tb(tfd, num_tbs, addr, len);
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+
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+ return 0;
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+}
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+
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+/*
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+ * Tell nic where to find circular buffer of Tx Frame Descriptors for
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+ * given Tx queue, and enable the DMA channel used for that queue.
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+ *
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+ * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
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+ * channels supported in hardware.
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+ */
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+static int iwlagn_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
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+{
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+ int txq_id = txq->q.id;
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+
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+ /* Circular buffer (TFD queue in DRAM) physical base address */
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+ iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
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+ txq->q.dma_addr >> 8);
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+
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+ return 0;
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+}
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+
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/**
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* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
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*/
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@@ -97,7 +246,7 @@ void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
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return;
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while (q->write_ptr != q->read_ptr) {
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- priv->cfg->ops->lib->txq_free_tfd(priv, txq);
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+ iwlagn_txq_free_tfd(priv, txq);
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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}
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@@ -391,7 +540,7 @@ int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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return ret;
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/* Tell device where to find queue */
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- priv->cfg->ops->lib->txq_init(priv, txq);
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+ iwlagn_tx_queue_init(priv, txq);
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return 0;
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err:
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@@ -420,7 +569,7 @@ void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
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/* Tell device where to find queue */
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- priv->cfg->ops->lib->txq_init(priv, txq);
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+ iwlagn_tx_queue_init(priv, txq);
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}
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/*************** HOST COMMAND QUEUE FUNCTIONS *****/
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@@ -553,9 +702,8 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
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trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
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- priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
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- phys_addr, fix_size, 1,
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- U32_PAD(cmd->len[0]));
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+ iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, fix_size, 1,
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+ U32_PAD(cmd->len[0]));
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/* Increment and update queue's write index */
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q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
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Johannes Berg