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ARMv7: Enable the SWP instruction

The SWP instruction has been deprecated starting with the ARMv6
architecture. On ARMv7 processors with the multiprocessor extensions
(like Cortex-A9), this instruction is disabled by default but it can be
enabled by setting bit 10 in the System Control register. Note that
setting this bit is safe even if the ARMv7 processor has the SWP
instruction enabled by default.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Catalin Marinas 16 gadi atpakaļ
vecāks
revīzija
213fb2a8ee
1 mainītis faili ar 4 papildinājumiem un 4 dzēšanām
  1. 4 4
      arch/arm/mm/proc-v7.S

+ 4 - 4
arch/arm/mm/proc-v7.S

@@ -232,14 +232,14 @@ __v7_setup:
 ENDPROC(__v7_setup)
 ENDPROC(__v7_setup)
 
 
 	/*   AT
 	/*   AT
-	 *  TFR   EV X F   I D LR
-	 * .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
+	 *  TFR   EV X F   I D LR    S
+	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
 	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
 	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-	 *    1    0 110       0011 1.00 .111 1101 < we want
+	 *    1    0 110       0011 1100 .111 1101 < we want
 	 */
 	 */
 	.type	v7_crval, #object
 	.type	v7_crval, #object
 v7_crval:
 v7_crval:
-	crval	clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
+	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
 
 
 __v7_setup_stack:
 __v7_setup_stack:
 	.space	4 * 11				@ 11 registers
 	.space	4 * 11				@ 11 registers