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@@ -1003,10 +1003,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
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fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
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rval = QLA_SUCCESS;
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- fw->hccr = RD_REG_DWORD(®->hccr);
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+ fw->host_status = RD_REG_DWORD(®->host_status);
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/* Pause RISC. */
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- if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) {
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+ if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) {
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET |
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HCCRX_CLR_HOST_INT);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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@@ -1021,16 +1021,54 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
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}
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}
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- /* Disable interrupts. */
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- WRT_REG_DWORD(®->ictrl, 0);
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- RD_REG_DWORD(®->ictrl);
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-
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if (rval == QLA_SUCCESS) {
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/* Host interface registers. */
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dmp_reg = (uint32_t __iomem *)(reg + 0);
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
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fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
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+ /* Disable interrupts. */
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+ WRT_REG_DWORD(®->ictrl, 0);
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+ RD_REG_DWORD(®->ictrl);
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+
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+ /* Shadow registers. */
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+ WRT_REG_DWORD(®->iobase_addr, 0x0F70);
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+ RD_REG_DWORD(®->iobase_addr);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0000000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
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+
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0100000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
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+
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0200000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
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+
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0300000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
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+
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0400000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
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+
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0500000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
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+
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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+ WRT_REG_DWORD(dmp_reg, 0xB0600000);
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+ dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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+ fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
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+
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/* Mailbox registers. */
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mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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@@ -1308,43 +1346,6 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
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for (cnt = 0; cnt < 16; cnt++)
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*iter_reg++ = RD_REG_DWORD(dmp_reg++);
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- WRT_REG_DWORD(®->iobase_addr, 0x0F70);
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- RD_REG_DWORD(®->iobase_addr);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0000000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0100000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0200000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0300000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0400000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0500000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
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-
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
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- WRT_REG_DWORD(dmp_reg, 0xB0600000);
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- dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
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- fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
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-
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/* Local memory controller registers. */
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iter_reg = fw->lmc_reg;
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WRT_REG_DWORD(®->iobase_addr, 0x3000);
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@@ -1677,7 +1678,7 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
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ha->fw_major_version, ha->fw_minor_version,
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ha->fw_subminor_version, ha->fw_attributes);
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- qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr);
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+ qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
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qla_uprintf(&uiter, "\nHost Interface Registers");
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
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@@ -1687,6 +1688,14 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
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qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
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}
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+ qla_uprintf(&uiter, "\n\nShadow Registers");
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+ for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
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+ if (cnt % 8 == 0)
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+ qla_uprintf(&uiter, "\n");
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+
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+ qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
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+ }
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+
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qla_uprintf(&uiter, "\n\nMailbox Registers");
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
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if (cnt % 8 == 0)
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@@ -1855,14 +1864,6 @@ qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
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qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
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}
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- qla_uprintf(&uiter, "\n\nShadow Registers");
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- for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
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- if (cnt % 8 == 0)
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- qla_uprintf(&uiter, "\n");
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-
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- qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
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- }
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-
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qla_uprintf(&uiter, "\n\nLMC Registers");
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for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
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if (cnt % 8 == 0)
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