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@@ -1180,6 +1180,10 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
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WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
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WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
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WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
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+
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+ /* at this point everything should be setup correctly to enable master */
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+ pci_set_master(rdev->pdev);
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+
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radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
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if (r) {
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