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@@ -1,11 +1,13 @@
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-/*arch/powerpc/platforms/8xx/mpc885ads_setup.c
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- *
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+/*
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* Platform setup for the Freescale mpc885ads board
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*
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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+ * Heavily modified by Scott Wood <scottwood@freescale.com>
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+ * Copyright 2007 Freescale Semiconductor, Inc.
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+ *
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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@@ -18,12 +20,12 @@
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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-#include <linux/root_dev.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/fs_uart_pd.h>
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#include <linux/fsl_devices.h>
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#include <linux/mii.h>
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+#include <linux/of_platform.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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@@ -36,34 +38,24 @@
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#include <asm/8xx_immap.h>
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#include <asm/commproc.h>
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#include <asm/fs_pd.h>
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-#include <asm/prom.h>
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+#include <asm/udbg.h>
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#include <sysdev/commproc.h>
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-static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi);
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-static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
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-static void init_scc3_ioports(struct fs_platform_info *ptr);
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+static u32 __iomem *bcsr, *bcsr5;
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#ifdef CONFIG_PCMCIA_M8XX
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static void pcmcia_hw_setup(int slot, int enable)
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{
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- unsigned *bcsr_io;
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-
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- bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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if (enable)
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- clrbits32(bcsr_io, BCSR1_PCCEN);
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+ clrbits32(&bcsr[1], BCSR1_PCCEN);
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else
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- setbits32(bcsr_io, BCSR1_PCCEN);
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-
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- iounmap(bcsr_io);
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+ setbits32(&bcsr[1], BCSR1_PCCEN);
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}
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static int pcmcia_set_voltage(int slot, int vcc, int vpp)
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{
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u32 reg = 0;
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- unsigned *bcsr_io;
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-
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- bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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switch (vcc) {
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case 0:
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@@ -98,334 +90,196 @@ static int pcmcia_set_voltage(int slot, int vcc, int vpp)
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}
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/* first, turn off all power */
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- clrbits32(bcsr_io, 0x00610000);
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+ clrbits32(&bcsr[1], 0x00610000);
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/* enable new powersettings */
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- setbits32(bcsr_io, reg);
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+ setbits32(&bcsr[1], reg);
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- iounmap(bcsr_io);
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return 0;
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}
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#endif
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-void __init mpc885ads_board_setup(void)
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-{
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- cpm8xx_t *cp;
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- unsigned int *bcsr_io;
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- u8 tmpval8;
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-
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-#ifdef CONFIG_FS_ENET
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- iop8xx_t *io_port;
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-#endif
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-
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- bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
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- cp = (cpm8xx_t *) immr_map(im_cpm);
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-
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- if (bcsr_io == NULL) {
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- printk(KERN_CRIT "Could not remap BCSR\n");
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- return;
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- }
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-#ifdef CONFIG_SERIAL_CPM_SMC1
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- clrbits32(bcsr_io, BCSR1_RS232EN_1);
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- clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
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- tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
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- out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
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- clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
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-#else
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- setbits32(bcsr_io, BCSR1_RS232EN_1);
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- out_be16(&cp->cp_smc[0].smc_smcmr, 0);
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- out_8(&cp->cp_smc[0].smc_smce, 0);
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-#endif
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-
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-#ifdef CONFIG_SERIAL_CPM_SMC2
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- clrbits32(bcsr_io, BCSR1_RS232EN_2);
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- clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
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- setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
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- tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
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- out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
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- clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
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-
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- init_smc2_uart_ioports(0);
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-#else
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- setbits32(bcsr_io, BCSR1_RS232EN_2);
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- out_be16(&cp->cp_smc[1].smc_smcmr, 0);
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- out_8(&cp->cp_smc[1].smc_smce, 0);
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-#endif
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- immr_unmap(cp);
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- iounmap(bcsr_io);
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-
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-#ifdef CONFIG_FS_ENET
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- /* use MDC for MII (common) */
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- io_port = (iop8xx_t *) immr_map(im_ioport);
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- setbits16(&io_port->iop_pdpar, 0x0080);
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- clrbits16(&io_port->iop_pddir, 0x0080);
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-
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- bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
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- clrbits32(bcsr_io, BCSR5_MII1_EN);
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- clrbits32(bcsr_io, BCSR5_MII1_RST);
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-#ifndef CONFIG_FC_ENET_HAS_SCC
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- clrbits32(bcsr_io, BCSR5_MII2_EN);
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- clrbits32(bcsr_io, BCSR5_MII2_RST);
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+struct cpm_pin {
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+ int port, pin, flags;
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+};
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-#endif
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- iounmap(bcsr_io);
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- immr_unmap(io_port);
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+static struct cpm_pin mpc885ads_pins[] = {
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+ /* SMC1 */
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+ {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
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+ {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
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+ /* SMC2 */
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+#ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
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+ {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
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+ {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
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#endif
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-#ifdef CONFIG_PCMCIA_M8XX
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- /*Set up board specific hook-ups */
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- m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
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- m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
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+ /* SCC3 */
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+ {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
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+ {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
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+ {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
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+ {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
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+ {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
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+ {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
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+ {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
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+
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+ /* MII1 */
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+ {CPM_PORTA, 0, CPM_PIN_INPUT},
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+ {CPM_PORTA, 1, CPM_PIN_INPUT},
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+ {CPM_PORTA, 2, CPM_PIN_INPUT},
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+ {CPM_PORTA, 3, CPM_PIN_INPUT},
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+ {CPM_PORTA, 4, CPM_PIN_OUTPUT},
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+ {CPM_PORTA, 10, CPM_PIN_OUTPUT},
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+ {CPM_PORTA, 11, CPM_PIN_OUTPUT},
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+ {CPM_PORTB, 19, CPM_PIN_INPUT},
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+ {CPM_PORTB, 31, CPM_PIN_INPUT},
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+ {CPM_PORTC, 12, CPM_PIN_INPUT},
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+ {CPM_PORTC, 13, CPM_PIN_INPUT},
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+ {CPM_PORTE, 30, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 31, CPM_PIN_OUTPUT},
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+
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+ /* MII2 */
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+#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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+ {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {CPM_PORTE, 16, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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+ {CPM_PORTE, 21, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 22, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 23, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 24, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 25, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 26, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 27, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 28, CPM_PIN_OUTPUT},
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+ {CPM_PORTE, 29, CPM_PIN_OUTPUT},
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#endif
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-}
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+};
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-static void init_fec1_ioports(struct fs_platform_info *ptr)
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+static void __init init_ioports(void)
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{
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- cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
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- iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
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-
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- /* configure FEC1 pins */
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- setbits16(&io_port->iop_papar, 0xf830);
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- setbits16(&io_port->iop_padir, 0x0830);
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- clrbits16(&io_port->iop_padir, 0xf000);
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-
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- setbits32(&cp->cp_pbpar, 0x00001001);
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- clrbits32(&cp->cp_pbdir, 0x00001001);
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+ int i;
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- setbits16(&io_port->iop_pcpar, 0x000c);
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- clrbits16(&io_port->iop_pcdir, 0x000c);
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+ for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
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+ struct cpm_pin *pin = &mpc885ads_pins[i];
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+ cpm1_set_pin(pin->port, pin->pin, pin->flags);
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+ }
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- setbits32(&cp->cp_pepar, 0x00000003);
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- setbits32(&cp->cp_pedir, 0x00000003);
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- clrbits32(&cp->cp_peso, 0x00000003);
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- clrbits32(&cp->cp_cptr, 0x00000100);
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+ cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
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+ cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
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+ cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
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+ cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
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- immr_unmap(io_port);
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- immr_unmap(cp);
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+ /* Set FEC1 and FEC2 to MII mode */
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+ clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
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}
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-static void init_fec2_ioports(struct fs_platform_info *ptr)
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+static void __init mpc885ads_setup_arch(void)
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{
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- cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
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- iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
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-
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- /* configure FEC2 pins */
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- setbits32(&cp->cp_pepar, 0x0003fffc);
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- setbits32(&cp->cp_pedir, 0x0003fffc);
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- clrbits32(&cp->cp_peso, 0x000087fc);
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- setbits32(&cp->cp_peso, 0x00037800);
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- clrbits32(&cp->cp_cptr, 0x00000080);
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-
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- immr_unmap(io_port);
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- immr_unmap(cp);
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-}
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+ struct device_node *np;
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-void init_fec_ioports(struct fs_platform_info *fpi)
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-{
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- int fec_no = fs_get_fec_index(fpi->fs_no);
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+ cpm_reset();
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+ init_ioports();
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- switch (fec_no) {
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- case 0:
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- init_fec1_ioports(fpi);
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- break;
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- case 1:
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- init_fec2_ioports(fpi);
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- break;
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- default:
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- printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
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+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
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+ if (!np) {
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+ printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
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return;
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}
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-}
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-static void init_scc3_ioports(struct fs_platform_info *fpi)
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-{
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- unsigned *bcsr_io;
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- iop8xx_t *io_port;
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- cpm8xx_t *cp;
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+ bcsr = of_iomap(np, 0);
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+ bcsr5 = of_iomap(np, 1);
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+ of_node_put(np);
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- bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
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- io_port = (iop8xx_t *) immr_map(im_ioport);
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- cp = (cpm8xx_t *) immr_map(im_cpm);
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-
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- if (bcsr_io == NULL) {
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+ if (!bcsr || !bcsr5) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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- /* Enable the PHY.
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- */
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- clrbits32(bcsr_io + 4, BCSR4_ETH10_RST);
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- udelay(1000);
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- setbits32(bcsr_io + 4, BCSR4_ETH10_RST);
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- /* Configure port A pins for Txd and Rxd.
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- */
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- setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
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- clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
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+ clrbits32(&bcsr[1], BCSR1_RS232EN_1);
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+#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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+ setbits32(&bcsr[1], BCSR1_RS232EN_2);
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+#else
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+ clrbits32(&bcsr[1], BCSR1_RS232EN_2);
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+#endif
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- /* Configure port C pins to enable CLSN and RENA.
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- */
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- clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
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- clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
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- setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
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+ clrbits32(bcsr5, BCSR5_MII1_EN);
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+ setbits32(bcsr5, BCSR5_MII1_RST);
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+ udelay(1000);
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+ clrbits32(bcsr5, BCSR5_MII1_RST);
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- /* Configure port E for TCLK and RCLK.
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- */
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- setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
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- clrbits32(&cp->cp_pepar, PE_ENET_TENA);
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- clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
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- clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
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- setbits32(&cp->cp_peso, PE_ENET_TENA);
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-
|
|
|
- /* Configure Serial Interface clock routing.
|
|
|
- * First, clear all SCC bits to zero, then set the ones we want.
|
|
|
- */
|
|
|
- clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
|
|
|
- setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
|
|
|
+#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
|
|
|
+ clrbits32(bcsr5, BCSR5_MII2_EN);
|
|
|
+ setbits32(bcsr5, BCSR5_MII2_RST);
|
|
|
+ udelay(1000);
|
|
|
+ clrbits32(bcsr5, BCSR5_MII2_RST);
|
|
|
+#else
|
|
|
+ setbits32(bcsr5, BCSR5_MII2_EN);
|
|
|
+#endif
|
|
|
|
|
|
- /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
|
|
|
- */
|
|
|
- clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
|
|
|
- /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
|
|
|
- * by H/W setting after reset. SCC ethernet controller support only half duplex.
|
|
|
- * This discrepancy of modes causes a lot of carrier lost errors.
|
|
|
- */
|
|
|
+#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
|
|
|
+ clrbits32(&bcsr[4], BCSR4_ETH10_RST);
|
|
|
+ udelay(1000);
|
|
|
+ setbits32(&bcsr[4], BCSR4_ETH10_RST);
|
|
|
|
|
|
- /* In the original SCC enet driver the following code is placed at
|
|
|
- the end of the initialization */
|
|
|
- setbits32(&cp->cp_pepar, PE_ENET_TENA);
|
|
|
- clrbits32(&cp->cp_pedir, PE_ENET_TENA);
|
|
|
- setbits32(&cp->cp_peso, PE_ENET_TENA);
|
|
|
+ setbits32(&bcsr[1], BCSR1_ETHEN);
|
|
|
|
|
|
- setbits32(bcsr_io + 4, BCSR1_ETHEN);
|
|
|
- iounmap(bcsr_io);
|
|
|
- immr_unmap(io_port);
|
|
|
- immr_unmap(cp);
|
|
|
-}
|
|
|
+ np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
|
|
|
+#else
|
|
|
+ np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
|
|
|
+#endif
|
|
|
|
|
|
-void init_scc_ioports(struct fs_platform_info *fpi)
|
|
|
-{
|
|
|
- int scc_no = fs_get_scc_index(fpi->fs_no);
|
|
|
+ /* The SCC3 enet registers overlap the SMC1 registers, so
|
|
|
+ * one of the two must be removed from the device tree.
|
|
|
+ */
|
|
|
|
|
|
- switch (scc_no) {
|
|
|
- case 2:
|
|
|
- init_scc3_ioports(fpi);
|
|
|
- break;
|
|
|
- default:
|
|
|
- printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
|
|
- return;
|
|
|
+ if (np) {
|
|
|
+ of_detach_node(np);
|
|
|
+ of_node_put(np);
|
|
|
}
|
|
|
-}
|
|
|
-
|
|
|
-static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr)
|
|
|
-{
|
|
|
- unsigned *bcsr_io;
|
|
|
- cpm8xx_t *cp;
|
|
|
-
|
|
|
- cp = (cpm8xx_t *) immr_map(im_cpm);
|
|
|
- setbits32(&cp->cp_pepar, 0x000000c0);
|
|
|
- clrbits32(&cp->cp_pedir, 0x000000c0);
|
|
|
- clrbits32(&cp->cp_peso, 0x00000040);
|
|
|
- setbits32(&cp->cp_peso, 0x00000080);
|
|
|
- immr_unmap(cp);
|
|
|
-
|
|
|
- bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
|
|
|
|
|
- if (bcsr_io == NULL) {
|
|
|
- printk(KERN_CRIT "Could not remap BCSR1\n");
|
|
|
- return;
|
|
|
- }
|
|
|
- clrbits32(bcsr_io, BCSR1_RS232EN_1);
|
|
|
- iounmap(bcsr_io);
|
|
|
+#ifdef CONFIG_PCMCIA_M8XX
|
|
|
+ /* Set up board specific hook-ups.*/
|
|
|
+ m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
|
|
|
+ m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
|
|
|
+#endif
|
|
|
}
|
|
|
|
|
|
-static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi)
|
|
|
+static int __init mpc885ads_probe(void)
|
|
|
{
|
|
|
- unsigned *bcsr_io;
|
|
|
- cpm8xx_t *cp;
|
|
|
-
|
|
|
- cp = (cpm8xx_t *) immr_map(im_cpm);
|
|
|
- setbits32(&cp->cp_pepar, 0x00000c00);
|
|
|
- clrbits32(&cp->cp_pedir, 0x00000c00);
|
|
|
- clrbits32(&cp->cp_peso, 0x00000400);
|
|
|
- setbits32(&cp->cp_peso, 0x00000800);
|
|
|
- immr_unmap(cp);
|
|
|
-
|
|
|
- bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
|
|
-
|
|
|
- if (bcsr_io == NULL) {
|
|
|
- printk(KERN_CRIT "Could not remap BCSR1\n");
|
|
|
- return;
|
|
|
- }
|
|
|
- clrbits32(bcsr_io, BCSR1_RS232EN_2);
|
|
|
- iounmap(bcsr_io);
|
|
|
+ unsigned long root = of_get_flat_dt_root();
|
|
|
+ return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
|
|
|
}
|
|
|
|
|
|
-void init_smc_ioports(struct fs_uart_platform_info *data)
|
|
|
-{
|
|
|
- int smc_no = fs_uart_id_fsid2smc(data->fs_no);
|
|
|
-
|
|
|
- switch (smc_no) {
|
|
|
- case 0:
|
|
|
- init_smc1_uart_ioports(data);
|
|
|
- data->brg = data->clk_rx;
|
|
|
- break;
|
|
|
- case 1:
|
|
|
- init_smc2_uart_ioports(data);
|
|
|
- data->brg = data->clk_rx;
|
|
|
- break;
|
|
|
- default:
|
|
|
- printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
|
|
- return;
|
|
|
- }
|
|
|
-}
|
|
|
+static struct of_device_id __initdata of_bus_ids[] = {
|
|
|
+ { .name = "soc", },
|
|
|
+ { .name = "cpm", },
|
|
|
+ { .name = "localbus", },
|
|
|
+ {},
|
|
|
+};
|
|
|
|
|
|
-int platform_device_skip(const char *model, int id)
|
|
|
+static int __init declare_of_platform_devices(void)
|
|
|
{
|
|
|
-#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
|
|
|
- const char *dev = "FEC";
|
|
|
- int n = 2;
|
|
|
-#else
|
|
|
- const char *dev = "SCC";
|
|
|
- int n = 3;
|
|
|
-#endif
|
|
|
-
|
|
|
- if (!strcmp(model, dev) && n == id)
|
|
|
- return 1;
|
|
|
+ /* Publish the QE devices */
|
|
|
+ if (machine_is(mpc885_ads))
|
|
|
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
-
|
|
|
-static void __init mpc885ads_setup_arch(void)
|
|
|
-{
|
|
|
- cpm_reset();
|
|
|
-
|
|
|
- mpc885ads_board_setup();
|
|
|
-
|
|
|
- ROOT_DEV = Root_NFS;
|
|
|
-}
|
|
|
-
|
|
|
-static int __init mpc885ads_probe(void)
|
|
|
-{
|
|
|
- char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
|
|
|
- "model", NULL);
|
|
|
- if (model == NULL)
|
|
|
- return 0;
|
|
|
- if (strcmp(model, "MPC885ADS"))
|
|
|
- return 0;
|
|
|
-
|
|
|
- return 1;
|
|
|
-}
|
|
|
-
|
|
|
-define_machine(mpc885_ads)
|
|
|
-{
|
|
|
- .name = "MPC885 ADS",
|
|
|
- .probe = mpc885ads_probe,
|
|
|
- .setup_arch = mpc885ads_setup_arch,
|
|
|
- .init_IRQ = m8xx_pic_init,
|
|
|
- .get_irq = mpc8xx_get_irq,
|
|
|
- .restart = mpc8xx_restart,
|
|
|
- .calibrate_decr = mpc8xx_calibrate_decr,
|
|
|
- .set_rtc_time = mpc8xx_set_rtc_time,
|
|
|
- .get_rtc_time = mpc8xx_get_rtc_time,
|
|
|
+device_initcall(declare_of_platform_devices);
|
|
|
+
|
|
|
+define_machine(mpc885_ads) {
|
|
|
+ .name = "Freescale MPC885 ADS",
|
|
|
+ .probe = mpc885ads_probe,
|
|
|
+ .setup_arch = mpc885ads_setup_arch,
|
|
|
+ .init_IRQ = m8xx_pic_init,
|
|
|
+ .get_irq = mpc8xx_get_irq,
|
|
|
+ .restart = mpc8xx_restart,
|
|
|
+ .calibrate_decr = mpc8xx_calibrate_decr,
|
|
|
+ .set_rtc_time = mpc8xx_set_rtc_time,
|
|
|
+ .get_rtc_time = mpc8xx_get_rtc_time,
|
|
|
+ .progress = udbg_progress,
|
|
|
};
|
Scott Wood