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@@ -2787,18 +2787,14 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
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POSTING_READ(reg);
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udelay(200);
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- /* On Haswell, the PLL configuration for ports and pipes is handled
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- * separately, as part of DDI setup */
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- if (!IS_HASWELL(dev)) {
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- /* Enable CPU FDI TX PLL, always on for Ironlake */
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- reg = FDI_TX_CTL(pipe);
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- temp = I915_READ(reg);
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- if ((temp & FDI_TX_PLL_ENABLE) == 0) {
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- I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
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+ /* Enable CPU FDI TX PLL, always on for Ironlake */
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+ reg = FDI_TX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ if ((temp & FDI_TX_PLL_ENABLE) == 0) {
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+ I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
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- POSTING_READ(reg);
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- udelay(100);
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- }
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+ POSTING_READ(reg);
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+ udelay(100);
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}
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}
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