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@@ -60,7 +60,8 @@ static inline void clear_page_cpu(void *page)
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" .set noreorder \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" daddiu %0, %0, 128 \n"
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- " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n" /* Prefetch the first 4 lines */
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+ " pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n"
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+ /* Prefetch the first 4 lines */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n"
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@@ -106,7 +107,8 @@ static inline void copy_page_cpu(void *to, void *from)
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" daddiu %0, %0, 128 \n"
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" daddiu %1, %1, 128 \n"
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- " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n" /* Prefetch the first 4 lines */
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+ " pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n"
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+ /* Prefetch the first 4 lines */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n"
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@@ -207,15 +209,18 @@ typedef struct dmadscr_s {
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u64 pad_b;
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} dmadscr_t;
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-static dmadscr_t page_descr[DM_NUM_CHANNELS] __attribute__((aligned(SMP_CACHE_BYTES)));
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+static dmadscr_t page_descr[DM_NUM_CHANNELS]
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+ __attribute__((aligned(SMP_CACHE_BYTES)));
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void sb1_dma_init(void)
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{
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int i;
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for (i = 0; i < DM_NUM_CHANNELS; i++) {
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- u64 base_val = (u64)CPHYSADDR(&page_descr[i]) | V_DM_DSCR_BASE_RINGSZ(1);
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- void *base_reg = (void *)IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
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+ const u64 base_val = CPHYSADDR(&page_descr[i]) |
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+ V_DM_DSCR_BASE_RINGSZ(1);
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+ volatile void *base_reg =
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+ IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
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__raw_writeq(base_val, base_reg);
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__raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
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@@ -225,14 +230,15 @@ void sb1_dma_init(void)
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void clear_page(void *page)
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{
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- u64 to_phys = (u64)CPHYSADDR(page);
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+ u64 to_phys = CPHYSADDR(page);
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unsigned int cpu = smp_processor_id();
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/* if the page is not in KSEG0, use old way */
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if ((long)KSEGX(page) != (long)CKSEG0)
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return clear_page_cpu(page);
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- page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
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+ page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
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+ M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
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page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
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__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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@@ -248,8 +254,8 @@ void clear_page(void *page)
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void copy_page(void *to, void *from)
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{
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- u64 from_phys = (u64)CPHYSADDR(from);
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- u64 to_phys = (u64)CPHYSADDR(to);
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+ u64 from_phys = CPHYSADDR(from);
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+ u64 to_phys = CPHYSADDR(to);
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unsigned int cpu = smp_processor_id();
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/* if any page is not in KSEG0, use old way */
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@@ -257,15 +263,16 @@ void copy_page(void *to, void *from)
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|| (long)KSEGX(from) != (long)CKSEG0)
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return copy_page_cpu(to, from);
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- page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
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+ page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
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+ M_DM_DSCRA_INTERRUPT;
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page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
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- __raw_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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+ __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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/*
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* Don't really want to do it this way, but there's no
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* reliable way to delay completion detection.
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*/
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- while (!(__raw_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
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+ while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
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& M_DM_DSCR_BASE_INTERRUPT))
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;
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__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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