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@@ -648,203 +648,6 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
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-#if 0
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-/*
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- * Set beacon timers
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- */
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-int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
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- const struct ath5k_beacon_state *state)
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-{
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- u32 cfp_period, next_cfp, dtim, interval, next_beacon;
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-
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- /*
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- * TODO: should be changed through *state
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- * review struct ath5k_beacon_state struct
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- *
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- * XXX: These are used for cfp period bellow, are they
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- * ok ? Is it O.K. for tsf here to be 0 or should we use
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- * get_tsf ?
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- */
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- u32 dtim_count = 0; /* XXX */
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- u32 cfp_count = 0; /* XXX */
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- u32 tsf = 0; /* XXX */
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-
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- ATH5K_TRACE(ah->ah_sc);
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- /* Return on an invalid beacon state */
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- if (state->bs_interval < 1)
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- return -EINVAL;
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-
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- interval = state->bs_interval;
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- dtim = state->bs_dtim_period;
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-
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- /*
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- * PCF support?
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- */
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- if (state->bs_cfp_period > 0) {
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- /*
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- * Enable PCF mode and set the CFP
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- * (Contention Free Period) and timer registers
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- */
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- cfp_period = state->bs_cfp_period * state->bs_dtim_period *
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- state->bs_interval;
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- next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
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- state->bs_interval;
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-
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- AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
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- AR5K_STA_ID1_DEFAULT_ANTENNA |
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- AR5K_STA_ID1_PCF);
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- ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
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- ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
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- AR5K_CFP_DUR);
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- ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
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- next_cfp)) << 3, AR5K_TIMER2);
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- } else {
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- /* Disable PCF mode */
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- AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
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- AR5K_STA_ID1_DEFAULT_ANTENNA |
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- AR5K_STA_ID1_PCF);
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- }
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-
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- /*
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- * Enable the beacon timer register
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- */
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- ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
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-
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- /*
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- * Start the beacon timers
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- */
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- ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &
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- ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
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- AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
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- AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
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- AR5K_BEACON_PERIOD), AR5K_BEACON);
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-
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- /*
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- * Write new beacon miss threshold, if it appears to be valid
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- * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
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- * and return if its not in range. We can test this by reading value and
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- * setting value to a largest value and seeing which values register.
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- */
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-
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- AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
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- state->bs_bmiss_threshold);
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-
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- /*
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- * Set sleep control register
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- * XXX: Didn't find this in 5210 code but since this register
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- * exists also in ar5k's 5210 headers i leave it as common code.
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- */
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- AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
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- (state->bs_sleep_duration - 3) << 3);
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-
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- /*
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- * Set enhanced sleep registers on 5212
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- */
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- if (ah->ah_version == AR5K_AR5212) {
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- if (state->bs_sleep_duration > state->bs_interval &&
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- roundup(state->bs_sleep_duration, interval) ==
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- state->bs_sleep_duration)
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- interval = state->bs_sleep_duration;
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-
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- if (state->bs_sleep_duration > dtim && (dtim == 0 ||
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- roundup(state->bs_sleep_duration, dtim) ==
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- state->bs_sleep_duration))
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- dtim = state->bs_sleep_duration;
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-
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- if (interval > dtim)
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- return -EINVAL;
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-
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- next_beacon = interval == dtim ? state->bs_next_dtim :
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- state->bs_next_beacon;
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-
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- ath5k_hw_reg_write(ah,
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- AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
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- AR5K_SLEEP0_NEXT_DTIM) |
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- AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
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- AR5K_SLEEP0_ENH_SLEEP_EN |
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- AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
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-
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- ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
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- AR5K_SLEEP1_NEXT_TIM) |
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- AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
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-
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- ath5k_hw_reg_write(ah,
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- AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
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- AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
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- }
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-
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- return 0;
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-}
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-
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-/*
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- * Reset beacon timers
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- */
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-void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
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-{
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- ATH5K_TRACE(ah->ah_sc);
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- /*
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- * Disable beacon timer
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- */
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- ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
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-
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- /*
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- * Disable some beacon register values
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- */
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- AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
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- AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
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- ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
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-}
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-
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-/*
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- * Wait for beacon queue to finish
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- */
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-int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
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-{
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- unsigned int i;
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- int ret;
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-
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- ATH5K_TRACE(ah->ah_sc);
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-
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- /* 5210 doesn't have QCU*/
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- if (ah->ah_version == AR5K_AR5210) {
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- /*
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- * Wait for beaconn queue to finish by checking
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- * Control Register and Beacon Status Register.
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- */
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- for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
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- if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
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- ||
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- !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
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- break;
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- udelay(10);
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- }
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-
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- /* Timeout... */
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- if (i <= 0) {
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- /*
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- * Re-schedule the beacon queue
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- */
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- ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
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- ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
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- AR5K_BCR);
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-
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- return -EIO;
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- }
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- ret = 0;
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- } else {
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- /*5211/5212*/
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- ret = ath5k_hw_register_timeout(ah,
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- AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
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- AR5K_QCU_STS_FRMPENDCNT, 0, false);
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-
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- if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
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- return -EIO;
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- }
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-
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- return ret;
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-}
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-#endif
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-
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/*********************\
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* Key table functions *
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