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@@ -796,20 +796,37 @@ static void svm_get_segment(struct kvm_vcpu *vcpu,
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var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
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var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
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- /*
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- * SVM always stores 0 for the 'G' bit in the CS selector in
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- * the VMCB on a VMEXIT. This hurts cross-vendor migration:
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- * Intel's VMENTRY has a check on the 'G' bit.
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- */
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- if (seg == VCPU_SREG_CS)
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+ switch (seg) {
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+ case VCPU_SREG_CS:
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+ /*
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+ * SVM always stores 0 for the 'G' bit in the CS selector in
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+ * the VMCB on a VMEXIT. This hurts cross-vendor migration:
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+ * Intel's VMENTRY has a check on the 'G' bit.
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+ */
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var->g = s->limit > 0xfffff;
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-
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- /*
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- * Work around a bug where the busy flag in the tr selector
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- * isn't exposed
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- */
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- if (seg == VCPU_SREG_TR)
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+ break;
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+ case VCPU_SREG_TR:
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+ /*
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+ * Work around a bug where the busy flag in the tr selector
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+ * isn't exposed
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+ */
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var->type |= 0x2;
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+ break;
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+ case VCPU_SREG_DS:
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+ case VCPU_SREG_ES:
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+ case VCPU_SREG_FS:
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+ case VCPU_SREG_GS:
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+ /*
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+ * The accessed bit must always be set in the segment
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+ * descriptor cache, although it can be cleared in the
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+ * descriptor, the cached bit always remains at 1. Since
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+ * Intel has a check on this, set it here to support
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+ * cross-vendor migration.
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+ */
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+ if (!var->unusable)
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+ var->type |= 0x1;
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+ break;
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+ }
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var->unusable = !var->present;
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}
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