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@@ -164,6 +164,15 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
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EVENT_CONSTRAINT_END
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};
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+static struct event_constraint intel_slm_event_constraints[] __read_mostly =
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+{
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+ FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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+ FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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+ FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF */
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+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
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+ EVENT_CONSTRAINT_END
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+};
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+
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static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
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@@ -886,6 +895,140 @@ static __initconst const u64 atom_hw_cache_event_ids
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},
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};
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+static struct extra_reg intel_slm_extra_regs[] __read_mostly =
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+{
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+ /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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+ INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffff, RSP_0),
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+ INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffff, RSP_1),
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+ EVENT_EXTRA_END
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+};
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+
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+#define SLM_DMND_READ SNB_DMND_DATA_RD
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+#define SLM_DMND_WRITE SNB_DMND_RFO
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+#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
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+
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+#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
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+#define SLM_LLC_ACCESS SNB_RESP_ANY
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+#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
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+
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+static __initconst const u64 slm_hw_cache_extra_regs
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+ [PERF_COUNT_HW_CACHE_MAX]
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+ [PERF_COUNT_HW_CACHE_OP_MAX]
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+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
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+{
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+ [ C(LL ) ] = {
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+ [ C(OP_READ) ] = {
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+ [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
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+ [ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
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+ },
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+ [ C(OP_WRITE) ] = {
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+ [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
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+ [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
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+ [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
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+ },
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+ },
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+};
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+
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+static __initconst const u64 slm_hw_cache_event_ids
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+ [PERF_COUNT_HW_CACHE_MAX]
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+ [PERF_COUNT_HW_CACHE_OP_MAX]
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+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
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+{
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+ [ C(L1D) ] = {
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+ [ C(OP_READ) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
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+ },
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+ [ C(OP_WRITE) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0,
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+ },
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+ },
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+ [ C(L1I ) ] = {
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+ [ C(OP_READ) ] = {
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+ [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
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+ [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
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+ },
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+ [ C(OP_WRITE) ] = {
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+ [ C(RESULT_ACCESS) ] = -1,
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+ [ C(RESULT_MISS) ] = -1,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0,
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+ },
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+ },
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+ [ C(LL ) ] = {
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+ [ C(OP_READ) ] = {
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+ /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
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+ [ C(RESULT_ACCESS) ] = 0x01b7,
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+ /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
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+ [ C(RESULT_MISS) ] = 0x01b7,
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+ },
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+ [ C(OP_WRITE) ] = {
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+ /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
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+ [ C(RESULT_ACCESS) ] = 0x01b7,
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+ /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
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+ [ C(RESULT_MISS) ] = 0x01b7,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
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+ [ C(RESULT_ACCESS) ] = 0x01b7,
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+ /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
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+ [ C(RESULT_MISS) ] = 0x01b7,
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+ },
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+ },
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+ [ C(DTLB) ] = {
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+ [ C(OP_READ) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
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+ },
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+ [ C(OP_WRITE) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ [ C(RESULT_ACCESS) ] = 0,
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+ [ C(RESULT_MISS) ] = 0,
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+ },
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+ },
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+ [ C(ITLB) ] = {
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+ [ C(OP_READ) ] = {
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+ [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
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+ [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
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+ },
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+ [ C(OP_WRITE) ] = {
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+ [ C(RESULT_ACCESS) ] = -1,
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+ [ C(RESULT_MISS) ] = -1,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ [ C(RESULT_ACCESS) ] = -1,
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+ [ C(RESULT_MISS) ] = -1,
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+ },
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+ },
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+ [ C(BPU ) ] = {
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+ [ C(OP_READ) ] = {
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+ [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
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+ [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
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+ },
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+ [ C(OP_WRITE) ] = {
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+ [ C(RESULT_ACCESS) ] = -1,
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+ [ C(RESULT_MISS) ] = -1,
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+ },
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+ [ C(OP_PREFETCH) ] = {
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+ [ C(RESULT_ACCESS) ] = -1,
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+ [ C(RESULT_MISS) ] = -1,
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+ },
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+ },
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+};
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+
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static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
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{
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/* user explicitly requested branch sampling */
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@@ -2180,6 +2323,21 @@ __init int intel_pmu_init(void)
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pr_cont("Atom events, ");
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break;
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+ case 55: /* Atom 22nm "Silvermont" */
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+ memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
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+ sizeof(hw_cache_event_ids));
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+ memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
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+ sizeof(hw_cache_extra_regs));
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+
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+ intel_pmu_lbr_init_atom();
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+
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+ x86_pmu.event_constraints = intel_slm_event_constraints;
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+ x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
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+ x86_pmu.extra_regs = intel_slm_extra_regs;
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+ x86_pmu.er_flags |= ERF_HAS_RSP_1;
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+ pr_cont("Silvermont events, ");
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+ break;
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+
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case 37: /* 32 nm nehalem, "Clarkdale" */
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case 44: /* 32 nm nehalem, "Gulftown" */
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case 47: /* 32 nm Xeon E7 */
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