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@@ -28,7 +28,8 @@
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#define FUSE_UID_LOW 0x108
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#define FUSE_UID_HIGH 0x10c
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#define FUSE_SKU_INFO 0x110
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-#define FUSE_SPARE_BIT 0x200
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+
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+#define TEGRA20_FUSE_SPARE_BIT 0x200
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int tegra_sku_id;
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int tegra_cpu_process_id;
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@@ -36,6 +37,8 @@ int tegra_core_process_id;
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int tegra_chip_id;
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enum tegra_revision tegra_revision;
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+static int tegra_fuse_spare_bit;
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+
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/* The BCT to use at boot is specified by board straps that can be read
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* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
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*/
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@@ -56,14 +59,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_A04] = "A04",
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};
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-static inline u32 tegra_fuse_readl(unsigned long offset)
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+u32 tegra_fuse_readl(unsigned long offset)
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{
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return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
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}
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-static inline bool get_spare_fuse(int bit)
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+bool tegra_spare_fuse(int bit)
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{
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- return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
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+ return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
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}
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static enum tegra_revision tegra_get_revision(u32 id)
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@@ -77,7 +80,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
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return TEGRA_REVISION_A02;
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case 3:
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if (tegra_chip_id == TEGRA20 &&
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- (get_spare_fuse(18) || get_spare_fuse(19)))
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+ (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
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return TEGRA_REVISION_A03p;
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else
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return TEGRA_REVISION_A03;
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@@ -99,10 +102,12 @@ void tegra_init_fuse(void)
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reg = tegra_fuse_readl(FUSE_SKU_INFO);
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tegra_sku_id = reg & 0xFF;
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- reg = tegra_fuse_readl(FUSE_SPARE_BIT);
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+ tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
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+
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+ reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_cpu_process_id = (reg >> 6) & 3;
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- reg = tegra_fuse_readl(FUSE_SPARE_BIT);
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+ reg = tegra_fuse_readl(tegra_fuse_spare_bit);
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tegra_core_process_id = (reg >> 12) & 3;
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reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
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