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@@ -122,8 +122,6 @@ enum {
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/* Host Flags */
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MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
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MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
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- /* SoC integrated controllers, no PCI interface */
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- MV_FLAG_SOC = (1 << 28),
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MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
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@@ -362,6 +360,7 @@ enum {
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MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
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MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
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MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
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+ MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
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/* Port private flags (pp_flags) */
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MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
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@@ -374,7 +373,7 @@ enum {
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#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
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#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
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#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
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-#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
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+#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
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#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
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#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
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@@ -652,7 +651,7 @@ static const struct ata_port_info mv_port_info[] = {
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.port_ops = &mv_iie_ops,
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},
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{ /* chip_soc */
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- .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC,
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+ .flags = MV_GENIIE_FLAGS,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = ATA_UDMA6,
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.port_ops = &mv_iie_ops,
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@@ -1254,7 +1253,7 @@ static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
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cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
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cfg |= (1 << 22); /* enab 4-entry host queue cache */
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- if (HAS_PCI(ap->host))
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+ if (!IS_SOC(hpriv))
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cfg |= (1 << 18); /* enab early completion */
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if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
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cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
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@@ -2225,7 +2224,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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* a bogus register value which can indicate HW removal or PCI fault.
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*/
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if (pending_irqs && main_irq_cause != 0xffffffffU) {
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- if (unlikely((pending_irqs & PCI_ERR) && HAS_PCI(host)))
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+ if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
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handled = mv_pci_error(host, hpriv->base);
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else
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handled = mv_host_intr(host, pending_irqs);
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@@ -2876,7 +2875,7 @@ static unsigned int mv_in_pcix_mode(struct ata_host *host)
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void __iomem *mmio = hpriv->base;
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u32 reg;
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- if (!HAS_PCI(host) || !IS_PCIE(hpriv))
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+ if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
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return 0; /* not PCI-X capable */
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reg = readl(mmio + MV_PCI_MODE_OFS);
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if ((reg & MV_PCI_MODE_MASK) == 0)
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@@ -3018,7 +3017,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
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break;
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case chip_soc:
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hpriv->ops = &mv_soc_ops;
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- hp_flags |= MV_HP_ERRATA_60X1C0;
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+ hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0;
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break;
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default:
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@@ -3062,12 +3061,12 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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if (rc)
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goto done;
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- if (HAS_PCI(host)) {
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- hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
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- hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
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- } else {
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+ if (IS_SOC(hpriv)) {
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hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
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hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
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+ } else {
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+ hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
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+ hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
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}
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/* global interrupt mask: 0 == mask everything */
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@@ -3093,7 +3092,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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mv_port_init(&ap->ioaddr, port_mmio);
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#ifdef CONFIG_PCI
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- if (HAS_PCI(host)) {
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+ if (!IS_SOC(hpriv)) {
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unsigned int offset = port_mmio - mmio;
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ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
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ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
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@@ -3113,7 +3112,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
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}
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- if (HAS_PCI(host)) {
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+ if (!IS_SOC(hpriv)) {
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/* Clear any currently outstanding host interrupt conditions */
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writelfl(0, mmio + hpriv->irq_cause_ofs);
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