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@@ -2097,6 +2097,7 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
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bool disable_mclk_switching;
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u32 mclk, sclk;
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u16 vddc, vddci;
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+ u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
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if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
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btc_dpm_vblank_too_short(rdev))
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@@ -2138,6 +2139,39 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
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ps->low.vddci = max_limits->vddci;
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}
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+ /* limit clocks to max supported clocks based on voltage dependency tables */
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+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
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+ &max_sclk_vddc);
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+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
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+ &max_mclk_vddci);
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+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
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+ &max_mclk_vddc);
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+
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+ if (max_sclk_vddc) {
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+ if (ps->low.sclk > max_sclk_vddc)
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+ ps->low.sclk = max_sclk_vddc;
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+ if (ps->medium.sclk > max_sclk_vddc)
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+ ps->medium.sclk = max_sclk_vddc;
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+ if (ps->high.sclk > max_sclk_vddc)
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+ ps->high.sclk = max_sclk_vddc;
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+ }
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+ if (max_mclk_vddci) {
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+ if (ps->low.mclk > max_mclk_vddci)
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+ ps->low.mclk = max_mclk_vddci;
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+ if (ps->medium.mclk > max_mclk_vddci)
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+ ps->medium.mclk = max_mclk_vddci;
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+ if (ps->high.mclk > max_mclk_vddci)
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+ ps->high.mclk = max_mclk_vddci;
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+ }
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+ if (max_mclk_vddc) {
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+ if (ps->low.mclk > max_mclk_vddc)
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+ ps->low.mclk = max_mclk_vddc;
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+ if (ps->medium.mclk > max_mclk_vddc)
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+ ps->medium.mclk = max_mclk_vddc;
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+ if (ps->high.mclk > max_mclk_vddc)
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+ ps->high.mclk = max_mclk_vddc;
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+ }
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+
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/* XXX validate the min clocks required for display */
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if (disable_mclk_switching) {
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