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@@ -140,6 +140,11 @@
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#define I82579_LPI_CTRL PHY_REG(772, 20)
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#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
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+/* EMI Registers */
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+#define I82579_EMI_ADDR 0x10
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+#define I82579_EMI_DATA 0x11
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+#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
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+
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/* Strapping Option Register - RO */
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#define E1000_STRAP 0x0000C
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#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
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@@ -1723,11 +1728,25 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
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/* Configure the LCD with the OEM bits in NVM */
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ret_val = e1000_oem_bits_config_ich8lan(hw, true);
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- /* Ungate automatic PHY configuration on non-managed 82579 */
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- if ((hw->mac.type == e1000_pch2lan) &&
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- !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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- msleep(10);
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- e1000_gate_hw_phy_config_ich8lan(hw, false);
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+ if (hw->mac.type == e1000_pch2lan) {
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+ /* Ungate automatic PHY configuration on non-managed 82579 */
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+ if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
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+ msleep(10);
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+ e1000_gate_hw_phy_config_ich8lan(hw, false);
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+ }
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+
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+ /* Set EEE LPI Update Timer to 200usec */
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+ ret_val = hw->phy.ops.acquire(hw);
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+ if (ret_val)
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+ goto out;
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+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
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+ I82579_LPI_UPDATE_TIMER);
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+ if (ret_val)
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+ goto release;
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+ ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
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+ 0x1387);
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+release:
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+ hw->phy.ops.release(hw);
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}
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out:
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