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@@ -2048,12 +2048,18 @@ static int init_csrows(struct mem_ctl_info *mci)
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edac_dbg(1, "MC node: %d, csrow: %d\n",
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pvt->mc_node_id, i);
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- if (row_dct0)
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+ if (row_dct0) {
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nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
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+ csrow->channels[0]->dimm->nr_pages = nr_pages;
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+ }
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/* K8 has only one DCT */
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- if (boot_cpu_data.x86 != 0xf && row_dct1)
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- nr_pages += amd64_csrow_nr_pages(pvt, 1, i);
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+ if (boot_cpu_data.x86 != 0xf && row_dct1) {
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+ int row_dct1_pages = amd64_csrow_nr_pages(pvt, 1, i);
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+
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+ csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
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+ nr_pages += row_dct1_pages;
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+ }
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mtype = amd64_determine_memory_type(pvt, i);
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@@ -2072,9 +2078,7 @@ static int init_csrows(struct mem_ctl_info *mci)
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dimm = csrow->channels[j]->dimm;
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dimm->mtype = mtype;
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dimm->edac_mode = edac_mode;
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- dimm->nr_pages = nr_pages;
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}
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- csrow->nr_pages = nr_pages;
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}
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return empty;
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